Power semiconductor device with an auxiliary gate structure

ABSTRACT

Power semiconductor devices in GaN technology include an integrated auxiliary (double) gate terminal and a pulldown network to achieve a normally-off (E-Mode) GaN transistor with threshold voltage higher than 2V, low gate leakage current and enhanced switching performance. The high threshold voltage GaN transistor has a high-voltage active GaN device and a low-voltage auxiliary GaN device wherein the high-voltage GaN device has the gate connected to the source of the integrated auxiliary low-voltage GaN transistor and the drain being the external high-voltage drain terminal and the source being the external source terminal, while the low-voltage auxiliary GaN transistor has the gate (first auxiliary electrode) connected to the drain (second auxiliary electrode) functioning as an external gate terminal. A pull-down network for the switching-off of the high threshold voltage GaN transistor may be formed by additional auxiliary low-voltage GaN transistors and resistive elements connected with the low-voltage auxiliary GaN transistor.

RELATED APPLICATION DATA

This application is a continuation-in-part of International ApplicationNo. PCT/EP2020/062710, filed May 7, 2020, which claims the benefit ofSer. No. 16/405,619, filed May 7, 2019, the disclosures of which areincorporated herein by reference in their entireties.

TECHNICAL FIELD

The present disclosure relates to a power semiconductor device, forexample to a hetero-structure aluminium gallium nitride/gallium nitride(AlGaN/GaN) high electron mobility transistor (HEMT) or rectifier.

BACKGROUND

A power semiconductor device is a semiconductor device used as a switchor rectifier in power electronics (e.g., dc to ac inverter for motorcontrol or dc to dc converter for switched-mode power supplies). A powersemiconductor device is usually used in “commutation mode” (i.e., it iseither on or off), and therefore has a design optimized for such usage.

In general, a power device has a rated voltage (i.e. the potentialdifference that the device has to withstand in the off-state between itsmain terminals) of over 20 V and conducts more than 100 mA duringon-state. More commonly the rating of a power device is above 60V andabove 1 A. These values make the power devices very different from thelow power devices, which operate with voltages below 5V and typicalcurrents of under 1 mA and more commonly in the range of μAs or sub μAs.Another differentiation between power devices and other types of devicessuch as low power or RF, is that they operate mainly with large signalsand they behave like switches. An exception to that is found in highvoltage or power amplifiers, which use specialised power transistors.

Silicon bipolar junction transistors (BJT), metal-oxide-semiconductorfield effect transistors (MOSFET) and insulated gate bipolar transistors(IGBT) are common types of power semiconductor switching devices. Theirapplication areas range from portable consumer electronics, domesticappliances, hybrid and electric cars, motor control and power suppliesto RF and microwave circuits and telecommunication systems.

Gallium Nitride (GaN) has increasingly been considered as a verypromising material for use in the field of power devices with thepotential to lead to increased power density, reduced on-resistance, andhigh frequency response. The wide band gap of the material (E_(g)=3.39eV) results in high critical electric field (E_(c)=3.3 MV/cm) which canlead to the design of devices with a shorter drift region, and thereforelower on-state resistance, if compared to a silicon-based device withthe same breakdown voltage [1]. The use of an AlGaN/GaN heterostructurealso allows the formation of a two-dimensional electron gas (2DEG) atthe hetero-interface where carriers can reach very high mobility (μ=2000cm²/(Vs)) values [1]. In addition, the piezopolarization charge presentat the AlGaN/GaN heterostructure, results in a high electron density inthe 2DEG layer (e.g. 1×10¹³ cm⁻²). These properties allow thedevelopment of High Electron Mobility Transistors (HEMTs) and Schottkybarrier diodes with very competitive performance parameters [2],[3]. Anextensive amount of research has focused on the development of powerdevices using AlGaN/GaN heterostructures.

However, the 2DEG which inherently exists at the AlGaN/GaNhetero-interface creates a challenge when attempting the design ofnormally-off rather than normally-on devices. Nonetheless, asnormally-off transistors are preferable in most power electronicapplications several methods have been proposed which can lead toenhancement mode devices, among them the use of metal insulatorsemiconductor structures [4], use of fluorine treatment [5], recessedgate structures [6] and use of a p-type cap layer [7][8]. Due to therelative maturity and controllability in the epitaxial growth of pGaNlayers compared to the other techniques, pGaN/AlGaN/GaN HEMTs areconsidered the leading structure for commercialization.

FIG. 1 shows schematically the cross section in the active area of astate of the art pGaN HEMT. The device shown is a lateral three-terminaldevice with an AlGaN/GaN heterostructure grown epitaxially on a standardsilicon wafer 4. A transition layer 3 is used to allow a high qualityGaN layer 2 to be grown despite the significant lattice mismatch betweenGaN and Si. Carbon p-type doping is often added in the GaN layer [9].Finally, a thin cap GaN layer 11 is typically added to form the gatewith a Magnesium (Mg) p-type doping density greater than 1×10¹⁹ cm⁻³.

A typical pGaN gate device has a threshold voltage of ˜1.5-2V and gateopening bias voltage of ˜8V. Threshold voltage and gate opening voltagein enhancement mode GaN devices are of great interest as problems suchas unwanted device turn-on when the device is supposed to be off mayoccur in operation if threshold voltage is low. Secondly, gate turn-onmay be a problem due to the non-insulated gate structure. It istherefore apparent that the pGaN gate device operates with a gatevoltage in the range of 2V to 8V and preferably between 5 to 7V, tominimise the on-state resistance of the device while ensuring a lowleakage through the gate (below the opening voltage).

In the state of the art device a trade-off exists between the thresholdvoltage of the device and the carrier density in the 2DEG of the deviceand consequently the device on-state resistance. A previous study hasshown that for a pGaN doping greater than 1×10¹⁹ cm⁻³ the thresholdvoltage cannot be significantly altered by the use of a different gatemetal or the thickness of the pGaN layer [10]. A narrow window ofoperation is therefore specified in these devices (with gate voltages inthe range of 4V to 7V with respect to the source) [11] unlike theirsilicon counterparts [12]. The lower boundary is defined by the gatebias needed to fully form the channel (2DEG) below the gate (this isreferred to as the threshold voltage, Vth), and the upper boundary islimited by the point at which the gate turns on and considerable currentstarts flowing through it.

Another area of interest in AlGaN/GaN HEMTs is their fast switchingcapability. The high mobility of carriers in the 2DEG and a shorterdrift region for a given breakdown due to higher critical electric fieldcan lead to very low drift region charge, Qgd. Furthermore, the devicegate charge Qg is about an order of magnitude lower than correspondingstate of the art silicon devices [11], [12]. Therefore, the GaN HEMTscan switch at much higher speeds than silicon MOSFETs. While this isbeneficial in many applications, it can lead to unwanted oscillationsdue to parasitic components present both at the device and circuit level[13]. A possible solution proposed in order to avoid the oscillatorybehaviour is to add an external gate resistance to the device in orderto reduce the dV/dt and dl/dt rate observed [13].

In [14], an attempt to enlarge the window of operation defined by thethreshold voltage and the opening of the pGaN/AlGaN junction has beenmade by varying the composition of the gate metal. This attempt resultedto be unsuccessful as discussed in [10] where it is showed that for apGaN doping greater than 1×10¹⁹ cm⁻³ the threshold voltage cannot besignificantly altered using a different gate metal or by altering thethickness of the pGaN layer.

In [16] a higher Vth on a P-gate technology has been obtained via‘Through Recessed and Regrowth Gate (TRRG)’ technique. This processtechnology is based on a complete removal of the AlGaN barrier layer andsubsequent regrowth of it by epitaxial regrowth. This demonstrates morestable threshold voltages at increasing temperatures and the possibilityto reach Vth as high as 2.3V by controlling the thickness of the AlGaNlayer. Although this is an interesting process technology to obtain astable threshold voltage, it does affect the Ron when a Vth>2V isachieved. Moreover, the high Vth solution presented in [16] does notaddress the problem of the Rg-related oscillations during the fastswitching of the high voltage transistor, nor the high gate leakage ofthe pGaN gate technology.

In [17] an integrated double-gate technology for achieving high Vth(>2.8V) is demonstrated. The double-gate technology suggested in [17] isbased on the integration of a high voltage normally-on (D-Mode) and lowvoltage normally-off (E-Mode) GaN transistors. In this configurationhowever, the two transistors are in series and the overall on-stateresistance will be therefore be affected by the series contribution ofthe on-state resistance of the low voltage device.

Other proposed double-gate technologies are present in literature andthey are so called as they feature a second gate electrode either on topof the gate passivation layer [18] or buried into the heterostructuresstack [19]. These devices mainly aim at improving the dynamicperformance of the transistors by alleviating the current collapsephenomenon. The current collapse phenomenon is in fact a currentreduction in the on-state, when the device is repeatedly stressed tohigh voltages in the off-state.

An attempt to increase the Vth of a normally-off (enhancementmode—E-Mode) GaN transistor using a circuit configuration with diodesand a second gate electrode is made in [20]. In this document the diodesare used as voltage shifters and are connected in series with the gateof the high-voltage GaN devices. A device where the voltage shifter isachieved with a transistor is also described. In this particular case,however, the drain terminal of the voltage-shifter-transistor isconnected with the high-voltage drain terminal of the GaN device. Theimplication of such connection is that the driving device will have tosustain the high voltage in blocking mode and therefore be designed as ahigh voltage transistor with a longer drift region than for alow-voltage device. The device will therefore have increased areaconsumption and reliability of this additional transistor has to betaken into account. In addition in [20] no mention is made of the upperboundary limitation.

Resistive loads connected between the gate and source of GaN HEMTs orPower MOSFETs in general are also known and their aim can vary fromreducing the oscillations during high voltage switching, protecting thedevice against electro-static discharge and in general ensuring a robustoperation. For example in the data sheet of the GaN Systems parts [21] a3 kΩ resistor is recommended to be added between the gate terminal (gatebus) and the source (or ground).

In U.S. Pat. No. 9,882,553B2 and U.S. Ser. No. 10/411,681B2 a devicewhich enlarges the operation window of a III-V semiconductor device isdescribed.

In U.S. Ser. No. 10/374,591B2 a gate drive circuit is described forcontrolling operation of a wide bandgap semiconductor switch.

In US2020007119A1 a voltage regulating circuit implemented in GaN HEMTtechnology in order to provide a stable output voltage suitable for usein applications such as GaN power transistor gate drivers and lowvoltage auxiliary power supplies for GaN integrated circuits isdescribed.

SUMMARY

It is the aim of this invention to propose a solution for a p-gate GaNE-Mode transistor for concomitantly (i) leads to a reduction in the gateleakage current (ii) an increase in the threshold voltage, and (iii) anincrease in the gate voltage operation window. The result of these threefeatures are (i) avoidance of turn-on retriggering during the turn-offand limitations of oscillations in certain turn-off conditions wherehigh dV/dt rates are present (ii) improves the switching performance ofthe overall configuration via an integrated pull-down network.

According to this invention we propose a GaN power device that has theability of a high threshold voltage, a significantly large gate voltageoperation range with less or no risk of p-GaN junction opening, andoscillation-free or oscillation-reduced switching behaviour. The detailsof this invention will be discussed considering but not limited to apGaN gate E-Mode technology.

GaN transistors that utilise this disclosure are intended but notlimited to applications in low to medium voltage range. The lowervoltage capability devices (<200V but higher than 20V) would be suitablefor point-of-load applications i.e. low voltage DC-DC converters for ITor consumer electronics applications. Such devices can also be used inlinear electronics to increase efficiency, a large market potentialhowever exists at the 600V range for applications such as power factorcorrection (PFC), un-interrupted power supplies (UPS), motor drives, andphotovoltaic (PV) system inverters. 600V GaN devices can also find useas chargers in hybrid electric vehicles (HEV) and/or electric vehicles(EV), a market which is growing at an enormous pace. GaN transistorswith breakdown capabilities up to 1.2 kV and power ratings which canreach 7.2 kW can lead to GaN transistors being used in EV and HEVconverters and inverters where the high frequency of operation willallow a reduction in system size, a parameter which is significant whenconsidering mobile systems. Ultimately, if the power rating is extendedenough GaN transistors could find application in wind turbines (1.7 kV).Recent applications which require reliable operation in the MHz regimesuch as wireless charging in both IT (mobile phones, laptop) andautomotive (EV, HEV) sectors may be very suitable for this disclosure.Additionally, applications beyond power conversion are also envisionedsuch as class D audio amplifiers.

Broadly speaking, the disclosure relates to power semiconductor devicesusing GaN technology. The disclosure proposes an integrated auxiliarygate terminal and a pulldown network to achieve a normally-off (E-Mode)GaN transistor with threshold voltage higher than 2V, low gate leakagecurrent and possibly enhanced switching performance. The high thresholdvoltage GaN transistor has a high-voltage active GaN device and anauxiliary GaN device, which could be preferably a low-voltage device,wherein the high-voltage GaN device has the gate connected to the sourceof the integrated auxiliary GaN transistor and the drain being theexternal high-voltage drain terminal and the source being the externalsource terminal, while the auxiliary GaN transistor has the gate (firstauxiliary electrode) connected to the drain (second auxiliary electrode)functioning as an external gate terminal. In other embodiments apull-down network for the switching-off of the high threshold voltageGaN transistor is formed by a diode, a resistor, or a parallelconnection of both connected in parallel with the auxiliary GaNtransistor.

In other embodiments a pull down network for the switching off of theactive (high voltage) GaN transistor is formed by additional auxiliarylow-voltage GaN transistors and resistive elements connected in parallelor in series with the low-voltage auxiliary GaN transistor.

In other embodiments, a pull down network for the switching off of theactive (high voltage) GaN transistor is formed by an active Millerclamp.

In other embodiments, an overvoltage protection circuit is formed byresistors or resistive elements and a low voltage enhancement mode (ordepletion mode) transistor to limit the maximum potential at the gate ofthe active (high voltage) transistor.

In other embodiments, an over-current protection circuit is formed by acurrent sensing resistor or resistive element and a low voltageenhancement mode (or an active depletion mode) transistor to act asprotection from over-current events.

According to a second aspect of this invention, there is provided aheterojunction (Gallium Nitride) chip (also named or termed as GaN chipor GaN power integrated circuit or GaN smart device or a GaN highvoltage integrated circuit) having at least three terminals, a highvoltage terminal, a low voltage terminal and a control terminal, andcontaining at least one high-voltage active GaN device (also referred toas main power heterojunction transistor) having an internal gate and,its source and drain connected to the low voltage and high voltageterminals of the GaN chip respectively, a pull-down circuit, anauxiliary gate circuit containing at least one low-voltageheterojunction transistor, and a current control circuit where:

the auxiliary gate circuit has one connection to the internal gate ofthe said at least one main power heterojunction transistor, a secondconnection to the control terminal, and at least one more connectionwhich links the gate of the at least one low-voltage heterojunctiontransistor to the pull down circuit;

-   -   the pull-down circuit has at least one connection to the current        control circuit and one connection to the source terminal of the        said at least one main power heterojunction transistor;

the current control circuit has one connection to the control terminaland where the auxiliary gate partly controls the voltage and the currentlevels into the internal gate of the at least one main powerheterojunction transistor, the current control circuit controls thecurrent level into the pull down circuit and in conjunction with thepull down circuit design determines the voltage level applied to thecontrol terminal at which the pull-down circuit actively pulls down thegate voltage of the said at least one low-voltage heterojunctiontransistor to clamp the voltage of the internal gate of the at least onemain power heterojunction transistor.

The integrated auxiliary gate block (circuit) in the GaN chip iscomposed of an auxiliary GaN transistor, which could be preferably alow-voltage device, wherein the high-voltage active GaN device (mainpower heterojunction transistor) has the gate connected to the source ofthe integrated auxiliary GaN transistor and the auxiliary GaN transistorhas the drain connected to the GaN chip control terminal.

The integrated current control block (circuit) is connected between thedrain and gate terminal of the auxiliary GaN transistor.

An integrated pull-down circuit block (circuit) is connected between thegate terminal of the auxiliary GaN transistor and the source terminal ofthe high voltage active GaN device.

The threshold voltage of the GaN chip (the potential applied to thecontrol terminal of the GaN chip with respect with its low voltageterminal at which the main power heterojunction transistor startsconducting current) could be higher than the intrinsic threshold voltageof the main power heterojunction transistor alone. This could beachieved by an additional voltage drop across the integrated auxiliarygate block when a voltage signal is applied on the control terminal ofthe GaN chip (also termed the external gate terminal). The potential onthe internal gate (also termed active gate terminal) is therefore lowerthan the potential applied to the control terminal of the GaN chip.

The voltage drop across the auxiliary gate block (circuit) is non-linearwhen the voltage signal on the external gate terminal (control terminal)increases linearly.

The low gate leakage current for the high voltage active GaN device(main power heterojunction transistor) is achieved by limiting thepotential on the internal gate (active gate) terminal. This is achievedby allowing for a voltage drop across the integrated auxiliary gateblock. The limit on the potential of the active gate terminal is definedby designing the current control block and pull-down circuit blockappropriately such that the gate of the auxiliary gate transistor ispulled down when the gate signal on the external gate terminal (controlterminal of the GaN chip) increases beyond a certain level. The gatevoltage operation window of the GaN chip (i.e. the voltage operationwindow applied to the control terminal) is therefore increased comparedto that of a conventional GaN HEMT.

The maximum voltage signal that can be applied to the external gate ofthe device (the control terminal of the GaN chip) can be designed to beabove 10V (e.g. 20V) such that conventional Silicon gate drivers andcontrollers can be used to drive the GaN chip.

Furthermore, the current control block (and other circuits) need to beappositely designed such that a balance between fast turn-on, avoidingovershoot of the active gate terminal (internal gate terminal) duringturn-on and a low gate driver power consumption during the on-stateoperation of the device is achieved.

The integrated current control circuit (current control block) may be aresistive element or incorporate a resistive element. Alternatively, thecurrent control circuit may be or comprise a current source. The currentsource may be composed of a low-voltage depletion mode HEMT and aresistive element. The resistive element can be connected between thegate and source terminal of the low-voltage depletion mode HEMT. Thedrain terminal of the depletion mode HEMT is connected to the drainterminal of the auxiliary gate HEMT and the gate terminal of thedepletion mode HEMT is connected to the gate terminal of the auxiliarygate HEMT.

In similar embodiments, an RCL network could be included in parallel tothe resistive element or the current source to improve the dynamiccharacteristic during the device turn-on or turn-off transients.

The current control block may further include a circuit creating anadditional voltage drop. The current control block may further include acircuit that adapts the current in the current control block dependingon the operating condition, such as switching, on or off condition. Sucha current adaption circuit may include a depletion mode HEMT or anenhancement mode HEMT in series or in parallel with the resistiveelement in the current source.

In some embodiments the integrated pull-down circuit (block) can be orcomprise one or several HEMTs in parallel or in series. The gatepotentials of said pull-down HEMTs are controlled to set the voltagedrop across the pull-down HEMT and therefore setting the gate voltage ofthe auxiliary gate block and the voltage drop across the auxiliary gateblock.

The pull-down circuit block may further comprise elements to compensateor reduce the effect of temperature on the voltage drop across thepull-down circuit block.

The pull-down circuit may comprise one or more diodes in series with aDC or actively switched voltage source. The diodes may be HEMT-diodes.

The diodes may comprise HEMT transistors having a source and gateconnected together. In this case, a gate voltage of the auxiliary gateblock is given by the voltage source and a voltage drop across the oneor more diodes.

In another embodiment, the auxiliary gate may include a low voltagedepletion mode transistor rather than a low voltage enhancement modetransistor. This embodiment might not be as effective in achieving anincreased threshold voltage for the GaN chip but can achieve anincreased operation range by allowing an increase in the maximumallowable control signal (external gate signal) level. The depletionmode GaN transistor might be used as part of the turn-off network of thedevice as the channel in the depletion mode transistor is present whenthe potential on the active gate is high and the potential at theexternal gate terminal is low.

In other embodiments, some or all of the functional blocks described canbe used together to add enhanced functionality.

Since the auxiliary GaN Transistor would preferably be a low voltagedevice, its source and drain terminal could be interchanged as they arecommonly made in a symmetrical (or similar) way. By a low-voltagedevice, we mean a device that can typically have a rated breakdown below20V and limited current capability (under 100 mA). However, it should beunderstood that the auxiliary gate could also be a high power or highvoltage device, although this may add cost and complexity.

Most of the embodiments according to this disclosure described here areconcerned with an integrated auxiliary transistor, whereby the auxiliarytransistor and the active transistor are made on the same substrate (inthe same chip). While the integration of the two could be advantageousfor several reasons, such as fewer pads, low area consumption, compactsize, lower cost and lower complexity, the auxiliary transistor couldalso be made on a separate substrate and connected to the activetransistor in a discrete or hybrid way. The auxiliary and the activetransistors could be placed side by side in the same package or moduleor discretely connected on a board and not necessarily integrated withinthe same GaN chip.

This could also apply to the other functional blocks described.

According to one aspect of the present disclosure, there is provided aIII-nitride semiconductor based heterojunction power device, comprising:

-   -   an active heterojunction transistor formed on a substrate, the        active heterojunction transistor comprising:        -   a first III-nitride semiconductor region comprising a first            heterojunction comprising an active two dimensional carrier            gas of second conductivity type;        -   a first terminal operatively connected to the III-nitride            semiconductor region;        -   a second terminal laterally spaced from the first terminal            and operatively connected to the III-nitride semiconductor            region;        -   an active gate region formed over the III-nitride            semiconductor region, the active gate region being formed            between the first terminal and the second terminal;    -   an auxiliary heterojunction transistor formed on the said        substrate or a further substrate, the auxiliary heterojunction        transistor comprising:        -   a second III-nitride semiconductor region comprising a            second heterojunction comprising an auxiliary two            dimensional carrier gas of second conductivity type;        -   a first additional terminal operatively connected to the            second III-nitride semiconductor region;        -   a second additional terminal laterally spaced from the first            additional terminal and operatively connected to the second            III-nitride semiconductor region;        -   an auxiliary gate region formed over the second III-nitride            semiconductor region, the auxiliary gate region being formed            between the first additional terminal and the second            additional terminal;    -   wherein the first additional terminal is operatively connected        with the auxiliary gate region, and wherein the second        additional terminal is operatively connected with the active        gate region,    -   wherein the auxiliary heterojunction transistor is a first        auxiliary heterojunction transistor, and wherein the        heterojunction power device further comprises a second auxiliary        heterojunction transistor which is operatively connected in        parallel with the first auxiliary transistor, and wherein the        first additional terminal of the first auxiliary heterojunction        transistor is operatively connected to a source terminal of the        second auxiliary heterojunction transistor, and the second        additional terminal of the first auxiliary heterojunction        transistor is operatively connected to a drain terminal of the        second auxiliary heterojunction transistor,    -   wherein the auxiliary heterojunction transistor is configured to        (or the addition of the auxiliary heterojunction transistor)        result in an increase in a threshold voltage of said        heterojunction power device and/or an increase in an operation        voltage range of the first additional terminal.

Here the term “operatively connected” means the terminals areelectrically connected. In other words, the first additional terminaland the auxiliary gate are electrically connected, and the secondadditional terminal and the active gate region are electricallyconnected. Furthermore, in one embodiment, the first terminal is asource terminal of the active transistor, and the second terminal is adrain terminal of the active transistor. On the other hand, the firstadditional terminal is a drain terminal of the auxiliary transistor andthe second additional terminal is a source terminal of the auxiliarytransistor. In embodiments, the connected first additional terminal andthe auxiliary gate region form a high voltage terminal (or form anexternal gate terminal) in which a relatively higher voltage is appliedcompared to the second additional terminal. Therefore, the secondadditional terminal can be termed as a low voltage terminal of theauxiliary transistor. Here the term “μl-nitride semiconductor region”generally refers to an entire region comprising a GaN layer and an AlGaNlayer formed on the GaN layer. The two dimensional carrier gas isgenerally formed at the interface between the GaN layer and the AlGaNlayer within the III-nitride semiconductor region. In embodiments, thetwo dimensional carrier gas refers to two dimensional electron gas(2DEG) or two dimensional hole gas (2DHG).

When integrated on the same substrate (monolithical integration), theheterojunction power device may further comprise an isolator regionbetween the active heterojunction transistor and the auxiliaryheterojunction transistor. The isolator region separates the active twodimensional carrier gas and the auxiliary two dimensional carrier gas.Isolator region may separate the first and second III-nitridesemiconductor regions.

In use, when the first additional terminal and the auxiliary gate regionmay be biased at a potential (or a voltage), a carrier density in aportion of the auxiliary two dimensional carrier gas underneath theauxiliary gate region is controlled such that an auxiliary twodimensional carrier gas connection is established between the first andsecond additional terminals. Generally, there is a two dimensionalelectron gas (2DEG) formed underneath the first and second additionalterminals. When a voltage is applied to the auxiliary gate region (orthe high voltage terminal), it controls the carrier density in the 2DEGunderneath the auxiliary gate so that a 2DEG connection is formedbetween the 2DEG underneath the first and second additional terminals.

The active gate region may be configured to be switched on through theauxiliary two dimensional carrier gas (e.g. 2DEG) connection between thefirst and second additional terminals. The resistance variation from the2DEG connection underneath the auxiliary gate region enables to turn onthe active gate as well. The auxiliary 2DEG connection may serve as aninternal resistance to the active gate region. Such an internal gateresistance could be useful to slow down the fast dV/dt during switchingor prevent high oscillations caused by di/dt effects.

The first additional terminal and the auxiliary gate region may beconfigured such that a part of the potential is used to form theauxiliary 2DEG connection and a further part of potential is used toswitch on the active gate region.

The first III-nitride semiconductor region may comprise an activealuminium gallium nitride (AlGaN) layer directly in contact with thefirst terminal, the active gate region and the second terminal.

The second III-nitride semiconductor region may comprise an auxiliaryaluminium gallium nitride (AlGaN) layer directly in contact with thefirst additional terminal, the auxiliary gate region and the secondadditional terminal.

The thickness of the active AlGaN layer and the auxiliary AlGaN layermay be the same or different.

The doping concentration of the active AlGaN layer and the auxiliaryAlGaN layer may be the same or different.

The aluminium mole fraction of the active AlGaN layer and the auxiliaryAlGaN layer may be the same or different.

The active gate region may comprise a p-type gallium nitride (pGaN)material. The metal contact on the active pGaN gate could be Schottky orohmic. Alternatively, the active gate region may comprise a recessedSchottky contact.

The first terminal, the second terminal, the first additional terminaland the second additional terminal may each comprise a surface ohmiccontact. Alternatively, the first terminal, the second terminal, thefirst additional terminal and the second additional terminal may eachcomprise a recessed ohmic contact.

The auxiliary gate region may comprise a field plate extending towardsthe first additional terminal and wherein the field plate extends over afield oxide region.

The power device may have an interdigitated layout in which a gate metalpad is directly connected with the auxiliary gate region and the firstadditional terminal, and the active gate region comprises gate fingersconnected with the second additional terminal.

Alternatively, the device may have an interdigitated layout in which theauxiliary gate region, the first additional terminal and the secondadditional terminal are placed below a source metal pad. Advantageously,no additional wafer area would be needed to include the auxiliary gatestructure compared to a state of the art design.

In embodiments, the second additional terminal and the active gateregion may be connected in a third dimension of the device.

The active heterojunction transistor may be a high voltage transistorand the auxiliary heterojunction transistor may be a low voltagetransistor compared to the active heterojunction transistor.

The heterojunction power device may further comprise a diode connectedin parallel between the first and second additional terminals of theauxiliary heterojunction transistor. The parallel diode acts as apull-down network during the turn-off of the overall configurationconnecting to ground from the gate terminal of the active GaNtransistor. When a positive bias (on-state) is applied to the auxiliarygate, the diode will be reverse-biased and zero current will flowthrough it, leaving unaffected the electrical behaviour of the overallhigh-voltage configuration. When a zero bias (off-state) will be appliedto the auxiliary gate the diode will forward bias and the turn-offcurrent flowing through it will discharge the gate capacitance of theactive transistor, thus enabling the switching off of the overallconfiguration. In off-state, the gate of the active transistor willremain biased to a minimum voltage equal to the turn-on voltage of thediode. The diode will therefore be designed in such a way that itsturn-on voltage will be as low as possible, ideally few mV. The diodemay be formed monolithically with the device. The diode could be asimple Schottky diode. The diode generally pulls down the active gateduring turn-off to the diode V_(th), therefore the diode needs to bedesigned to have as low a threshold voltage as possible. A feature whichcan achieve this is the use of a recessed anode such that the contact ismade directly to the 2DEG.

Alternatively, a normally-on (depletion mode) GaN power device not inprior art may be utilized. This normally-on device may contain a gatestructure based on discontinuous p-GaN layer (or discontinuous regionsof first conductivity type) containing islands within stripes or closedshapes around the cells that act to modulate the conductive path, givenby the 2D electron gas (or the 2D carrier gas of the second conductivitytype) between the high voltage terminal and low voltage terminal, when agate voltage is provided. All such islands may be connected to the samegate electrode. It will be appreciated that by discontinuous islands wemean that between adjacent islands there is no p-GaN layer present, andas such, there is a direct, unobstructed conductive path between thesource and the drain terminals, provided by the 2D electron gas.However, adjacent islands are placed closed together across (orthogonalto) the current path such that the potential applied to the p-GaN gateislands modulate the conductive region between the islands and thusmodulate the direct path between the source and the drain. The p-GaNlayers in the continuous and discontinuous gate structures are done inthe same process step and the difference between continuous anddiscontinuous is realized by a layout change of the same mask.

The operation of this normally on (depletion mode) device may becharacterised by the existence of two threshold voltages. The firstthreshold voltage may be negative and is equivalent to that of aclassical normally-on transistor, indicating the transition from the offto on-state. The second threshold voltage is preferably positive and ischaracterised by a steep current increase. The second threshold voltagecan occur at the same value as that of an integrated normally-off devicefeaturing a continuous p-GaN gate.

Two threshold voltages are clearly discussed and identified below ingreater detail.

The first threshold voltage referred to here as the device thresholdvoltage may be adjusted through layout modifications in addition toepitaxy/process modifications. Furthermore, the depletion mode (normallyon) device proposed here may allow for an increased positive gate biasvoltage to be applied (>7V) before the main on-state conduction channelchanges from drain-source to gate-source. Such a device can beimplemented in a fabrication process which does not offer a Schottkycontact on the surface of the AlGaN layer.

Alternatively, the normally on depletion device using discontinuous pGaNislands could be used in a diode mode, by connecting the gate and sourcetogether, which becomes the anode terminal (or because of the symmetryby connecting the drain and gate together). The distance (pitch) betweenthe pGaN islands could be used to adjust the voltage level at which thediode conducts current in the forward mode. This is particularlyadvantageous over the prior art where a continuous pGaN layer is usedwhich could result in a large forward voltage. For example, the pitchbetween pGaN islands (or multiple stripes of pGaN islands) could be usedto adjust this opening forward voltage to be 0.3 to 0.5V, which isspecific to Schottky diodes in silicon. To avoid a negative openingvoltage, which is undesirable for a diode, the pitch between the pGaNislands should be very small (orders of tens or hundreds of nanometres),or the source of the HEMT connected in the diode configuration canfeature a Schottky contact.

A second increase in the current is present at a higher voltage level(higher than the opening voltage level) during forward conduction, whenthe 2DEG under the pGaN layer is formed. It is desirable that in forwardconduction, the diode operates beyond this second voltage level tominimise the on-state resistance.

In all embodiments, the contact to the pGaN islands could be made ofohmic or Schottky metallisation.

The depletion mode III-nitride semiconductor based heterojunction devicemay further comprise at least two rows of active gate regions eachformed over the at least two highly doped semiconductor regions; whereinthe depletion mode III-nitride semiconductor based heterojunction devicehas two threshold levels, and wherein the depletion mode III-nitridesemiconductor based heterojunction device is configurable to activelyswitch between: (i) an off-state, wherein the gate voltage with respectto the source voltage is lower than the first threshold; (ii) a highresistance mode, wherein the gate voltage with respect to the sourcevoltage is between the first and second threshold levels; and (iii) alow resistance mode, wherein the gate voltage with respect to the sourcevoltage is higher than the second threshold.

In an embodiment, the described p-GaN islands are arranged in such a waythat the conductive path at a gate voltage between the first and secondthreshold levels follows a meander shape or labyrinth shape to increasethe length of the path and therefore the resistance between the mainterminals (source and drain) in a given area. When the potential appliedto the gate with respect to the source exceeds the second threshold, themeander shape or labyrinth shape is removed by activating the 2DEGunderneath the p-GaN islands, leading to a strong decrease in theresistance between source and drain. In this case the current flowsstraight (in one dimension) from the drain to the source and no longerin a meander shape (two dimensions). Therefore, this transistor canactively switch between an (i) off-state (e.g. negligible currentflowing through the source and drain) when the gate voltage with respectto the source voltage is lower than the first threshold, to (ii) a highresistance mode (meander shape of the current) when the gate voltagewith respect to the source voltage is between the first and secondthreshold levels to (iii) a low resistance mode when the gate voltagewith respect to the source voltage is higher than the second threshold.

The described D-HEMT with p-GaN islands, when in the high resistancemode described above (when the gate-source voltage is higher than thefirst threshold voltage, but lower than the second threshold voltage),may feature a saturation (or quasi-saturation) current behaviourlimiting the current at strong forward bias. The extent to which thecurrent saturates may be affected by the distance between the pGaNislands where the smaller the distance between the pGaN islands, thestronger the current saturation observed. An example of this saturationis illustrated in FIG. 71. As the drain increases, the electric filedincreases, forming a depletion region which limits the current flowingin the meander shape, as the current is now constricted by the depletionregion. The obstruction of current is even more prominent between thegaps of the p-GaN islands.

A D-HEMT of this type may be used as an active Miller clamp transistorconnected between the gate and source terminal of the activeheterojunction transistor. When the active heterojunction transistor isin the on-state, the Miller clamp may be in the high resistance modedescribed. At strong forward bias of the Miller clamp transistor (thatis when the gate-source bias of the active heterojunction transistor isfor example at 6V) the current saturation observed may be desirable asit can limit the current from the gate terminal to the source terminalof the active heterojunction transistor and thus limit gate driverlosses. The resistance of the Miller clamp transistor may be lower (butstill in high resistance mode) at weak forward bias and therefore mayserve as protection during transient or switching events. The Millerclamp transistor may be in the low resistance mode described above whenthe active heterojunction transistor is in the off-state.

The first additional terminal (or the drain (gate) terminal) and thesecond additional terminal (or the source terminal) of the (first)auxiliary heterojunction transistor may each act as external gateterminals.

The heterojunction power device may further comprise measures to reduceunwanted electrical coupling or electrical interference between theactive heterojunction power transistor (active GaN device or main powerHEMT) and the auxiliary heterojunction transistor (auxiliary gatestructure). Such interference can be in the form of leakage currents,displacement currents, capacitive or inductive coupling from the activeGaN device to the auxiliary gate structure.

Accordingly, the heterojunction power device may further comprise ashielding and/or decoupling structure formed between the activeheterojunction transistor and the auxiliary heterojunction transistor.

The shielding and/or decoupling structure may comprise any of: one ormore layers of two-dimensional carrier gas of the first and/or secondconductivity type; one or more metal layers; and/or one or moreconductive layers; and the shielding and/or decoupling structure may beoperatively connected to one of: the first terminal; a potential; orground.

The shielding and/or decoupling structures may comprise one or morelayers of two-dimensional carrier gas of the first and/or secondconductivity type; one or more metal layers; and/or one or moreconductive layers between the active heterojunction power transistor(active GaN device) and the auxiliary heterojunction transistor(auxiliary structures). The shielding and/or decoupling structures maybe connected to the first terminal or any other suitable electricalpotential (such as ground). The shielding and/or decoupling structuresmay be placed around, below, above, on the sides and/or in the vicinityof any of the auxiliary heterojunction transistors (auxiliary gatestructures) or the active heterojunction power transistor (GaN activedevice).

Said conductive layers may comprise two-dimensional carrier gases (e.g.2DEG), metals, poly-silicon, Ill-nitride semiconductors, othersemiconductors or any other conductive materials. In an example, theheterojunction power device may comprise a 2DEG structure operativelyconnected to the first terminal and placed at least partially around theauxiliary GaN structure. In this example the 2DEG is connected to anappropriate potential (e.g. ground) in order to reduce the resistive andcapacitive coupling from the active GaN HEMT through the substrate orIII-nitride semiconductor region to the auxiliary gate structure orcircuitry.

Shielded structures may be capacitors, resistors, HEMTs or any otheractive and passive devices on the chip.

The shielding and/or decoupling structures may be formed between anyblocks of the circuit to isolate the respective blocks from theinfluence of each other.

In the present disclosure, the auxiliary heterojunction transistor is afirst auxiliary heterojunction transistor, and the heterojunction devicefurther comprises a second auxiliary heterojunction transistor which isoperatively connected in parallel with the first auxiliary transistor,and the first additional terminal (or the drain (gate) terminal) of thefirst auxiliary heterojunction transistor may be connected to a sourceterminal of the second auxiliary heterojunction transistor, and thesecond additional terminal (or the source terminal) of the firstauxiliary heterojunction transistor may be operatively connected to adrain (gate) terminal of the second auxiliary heterojunction transistor.

The pull-down network through the second auxiliary heterojunctiontransistor may further comprise of a resistor added in series with thesecond auxiliary transistor between the gate and drain terminal of thesecond auxiliary transistor. The resistor is between the gate and drainterminals of the second auxiliary transistor. Therefore the resistordoes not form a common junction between the first auxiliary transistorand the gate of the active transistor. The resistor acts to reduce theactive gate capacitance discharge time through the pull-down networkduring the turn-off of the heterojunction power device. The additionalresistive element performs this function by leading to an increasedpotential, during turn-off, of the second auxiliary transistor gateterminal compared to the second auxiliary transistor drain terminal. Anadditional resistor could be connected between the drain terminal of thesecond auxiliary transistor and the source terminal of the active powertransistor. The additional resistor acts as a parallel pull-down networkduring the active device turn-off. Therefore, it will be understood thatthe additional resistor is not connected through a common junctionconnecting the source of the first auxiliary transistor and the gate ofthe active transistor. During the active device turn-on and on-state theadditional resistor can act as a voltage limiting component to protectthe gate terminal of the active device.

The pull-down network through the second auxiliary heterojunctiontransistor may further comprise of a third auxiliary transistor added inseries with the second auxiliary transistor between the gate and drainterminal of the second auxiliary transistor. The third auxiliarytransistor acts to reduce the active gate capacitance discharge timethrough the pull-down network during the turn-off of the heterojunctionpower device. The third auxiliary transistor performs this function byleading to an increased potential, during turn-off, of the secondauxiliary transistor gate terminal compared to the second auxiliarytransistor drain terminal. The third auxiliary transistor may be adepletion mode low-voltage transistor. The depletion mode device couldbe made using p-GaN islands as shown in FIG. 18, or could be a diode asshown in FIG. 19. The gate terminal of the third auxiliary transistormay be connected to either the source or drain terminal of the thirdauxiliary transistor. An additional resistor could be connected betweenthe drain terminal of the second auxiliary transistor and the sourceterminal of the active (high voltage) transistor. In other words, itwill be understood that the additional resistor is not connected througha common junction connecting the source of the first auxiliarytransistor and the gate of the active transistor. The additionalresistor acts as a parallel pull-down network during the active deviceturn-off. During the active device turn-on and on-state the additionalresistor can act as a voltage limiting component to protect the gateterminal of the active device.

The heterojunction power device may further comprise a voltage limitingcircuit composed of two resistors forming a potential divider and anactively switched low voltage enhancement mode transistor. The drainsource path of the actively switched low voltage enhancement modetransistor is connected between the gate and source of the active powertransistor. The potential divider is connected between the firstadditional terminal (or the drain (gate) terminal) of the firstauxiliary heterojunction transistor and the source terminal of theactive (high voltage) transistor. The mid-point of the potential divideris connected to the gate terminal of the low voltage enhancement modetransistor. The enhancement mode transistor can turn-on, and thus adjustthe resistance between the active device gate terminal and the active(high voltage) device source terminal, when the voltage of the firstadditional terminal (or the drain (gate) terminal) of the firstauxiliary heterojunction transistor is raised above a certain valuewhich can be controlled by the choice of resistors in the potentialdivider described. This function can protect the active gate terminalfrom over-voltage events.

The heterojunction power device may further comprise a voltage limitingcircuit as described above where the low voltage enhancement modetransistor is replaced with a low voltage depletion mode transistor. Inthis embodiment, the resistance of the depletion mode transistor can bereduced, and thus adjust the resistance between the active (highvoltage) device gate terminal and the active device source terminal,when the potential of the first additional terminal (or the drain (gate)terminal) of the first auxiliary heterojunction transistor is increased.The potential divider formed by the resistors determines the potentialon the gate terminal of the depletion mode transistor. The circuitdescribed can protect the active gate terminal from over-voltage events.

The heterojunction power device may further comprise an over-currentprotection circuit composed of a current sensing resistor and anactively switched low voltage enhancement mode transistor. The activearea of the active (high voltage) transistor is divided into two regionsforming two transistors in parallel. The drain and gate terminals of thetwo transistors are electrically connected. The two transistors inparallel are a low resistance (main power) transistor and a highresistance (current sensing) transistor comparatively. The firstterminal of the current sensing resistor is connected to the sourceterminal of the high resistance transistor. The actively switchedenhancement mode transistor is connected between the gate terminal ofthe active (high voltage) transistors and the second terminal of thecurrent sensing resistor. The gate terminal of the low voltageenhancement mode transistor is connected to the first terminal of thecurrent sensing resistor. As current through the high resistancetransistor increases, the potential drop across the current sensingresistor increases, raising the potential on the gate of the low voltageenhancement mode resistor and thus adjusting its resistance. A criticalcurrent through the low voltage transistor can turn on the low voltageenhancement mode transistor limiting the potential on the gate of theactive power transistors. The circuit described can protect the circuitfrom over-current events. The components described can be included inthe design monolithically.

The heterojunction power device may further comprise an over-currentprotection circuit as described above where the low voltage enhancementmode transistor is replaced with a low voltage depletion modetransistor. Similarly, the potential at the gate terminal of thedepletion mode transistor is increased as the current through thecurrent sensing resistor is increased. As the current through thecurrent sensing resistor increases the resistance of the depletion modetransistor can decrease providing a reduction in the resistance of thepath between the gate and source of the active (high voltage) devicesthus limiting the potential on the active gate terminal. The circuitdescribed can protect the circuit from an over-current event.

The heterojunction power device may further comprise an active Millerclamp to offer an additional pull-down network for the active (highvoltage) device gate terminal during the device turn-off transient. Theactive Miller clamp consists of a logic inverter and an activelyswitched transistor which acts as the pull down network. The logicinverter could be composed of a resistor or resistive element (i.e. loadtransistor) and an enhancement mode transistor.

In some embodiments, the logic inverter may comprise a current sourcecircuit in series with an enhancement mode transistor in which thecurrent source may comprise a depletion mode transistor and a resistiveelement.

In some embodiments, the logic inverter may comprise of two or morestages. In a multi-stage inverter, all stages comprise an enhancementtransistor on the low side with the gate connected to the input signal.All stages comprise a pull-up circuit, of which all but the one of thefirst stage are at least partially controlled by the previous stages. Inone embodiment of a multi-stage inverter, the pull-up circuit of thefirst stage comprises a current source as described above. The pull-upcircuit of the second stage comprises a resistive element and adepletion-mode transistor in series where the gate of the depletion-modetransistor is connected to the output of a previous stage. In such amulti-stage inverter, the first stage can be realised with smallcomponents, leading to small capacitance and therefore a fast switchingtime even at small currents. Therefore, the gate of the depletion-modetransistor of the pull-up circuit of the subsequent stage may risefaster than in a current source arrangement. Therefore, this arrangementmay lead to a faster switching time at a given load and a given currentconsumption.

In a further embodiment of a multi-stage inverter, an additionaldepletion or enhancement transistor is connected to the pull-up circuitof the second or subsequent stages. This additional transistor has thegate connected to the output of a previous stage. The additionaltransistor may be connected in parallel to the pull-up circuit or inparallel to the resistive element of the pull-up circuit and may furtherincrease the current during switching when the output of one stage ishigher than the output of the subsequent stage. The increased currentduring switching leads to a faster switching time for a given load, suchas the actively switched transistor of a Miller clamp.

The actively switched transistor could be an enhancement mode ordepletion mode transistor. In operation the active Miller clamp uses thevoltage bias of the external gate terminal (i.e. the terminal connectedto the gate driver) to adjust the resistance of the actively switchedtransistor such that a low resistance pull-down path is provided whenthe main power device is turning-off or is in the off-state. When thegate driver signal is high, the bias on the gate of the activelyswitched transistor in the Miller clamp is low (therefore its resistanceis high) and vice versa.

The logic inverter of the active Miller clamp may be connected to a DCvoltage source through a decoupling circuit.

The decoupling circuit may comprise one or more resistors, capacitors,current sources, or other low voltage transistors

The role of the decoupling circuit is to protect the inverter fromcurrent spikes or voltage excursions induced from the voltage source.These current spikes or voltage excursions may be a result of capacitiveor magnetic coupling of the circuit to other elements of the chip or thesystem and exacerbated by fast transient voltages and/or currents.

In one embodiment, the decoupling circuit may comprise of a seriesresistor and a capacitor across the input voltage of the inverter. Inanother embodiment, the decoupling circuit comprise a current sourceformed of a depletion HEMT and a resistive element. In otherembodiments, a transistor may be added to the current source in parallelto the current source or in parallel to the resistive element to adjustthe current limit through the current source. In another embodiment, atransistor may be added in parallel to the capacitor to sink the currentin case of a current spike.

The described decoupling circuits may be used not only to protect theinverter but other circuits within the auxiliary gate interface.

The heterojunction chip may comprise at least one low voltage transistorthat is configured to ENABLE or DIASBLE the heterojunction chip, whereinthe ENABLE function permits the operation of the heterojunction chip asnormal, and wherein the DISABLE function transforms the chip into a highimpedance mode state, disabling the operation of the heterojunctionchip.

In a power electronics application, there may be the need to permanentlyor temporarily disable or enable the active HEMT, independent of thecontrol signal applied. Examples for the use of a disable or enablefunction are gate drivers, external controllers, undervoltage lock-out,start-up conditions, zero-voltage switching, overvoltage protection,overcurrent protection or other safety features. Some embodiments ofthis invention comprise an enable or disable function. The input signalto the disable or enable function could be generated internally on thechip or externally and may be the output of a sensing function.

The ENABLE function permits the operation of the heterojunction chip asnormal, while the DISABLE function transform the chip into a highimpedance mode state (HiZ), disabling its operation.

In one embodiment, the enable or disable function may be realised by atransistor connected between the gate and source of the active HEMT.Turning on said transistor disables the active HEMT.

In another embodiment, the enable function may be realised by atransistor connected in series with the Miller clamp transistor. Thiscreates a logic NAND function in the sense that both the Miller clamptransistor and the additional series transistor need to be on to turnoff the active HEMT.

In another embodiment, the enable or disable function may be realised aspart of the inverter connected to the Miller clamp transistor. A disableor enable transistor may be connected in series or in parallel with thelow-side enhancement transistors of the inverter. Further, the disableor enable function may be integrated with any other buffer or inverterblock of the circuit, transforming them into logic gates.

In another embodiment of the disable or enable function a disable orenable transistor is connected to the gate of the auxiliary HEMT. Theadditional transistor would short out partially or completely thepull-down circuit when in the low-resistive state and therefore keepingthe active HEMT off. Or, in other words, only when the additionaltransistor is in a high resistive state the active HEMT is enabled.

In all embodiments of the enable or disable function, the gate of theenable or disable transistor may be driven by an external signaldirectly or through a signal conditioning circuit such as inverter,buffer, voltage follower, Schmidt trigger, amplifier, voltage divider,protection circuit or latching circuit. Further, the gate of the enableor disable transistor may be driven by a signal generated on the chipsuch as signal conditioning or a sensing signal. Further, one or severaltransistors in series or in parallel may be used.

The resistor (in any of the embodiments shown here) could be made of ametal layer in the process, the AlGaN layer or preferably of the 2DEG.The resistor could be shaped in a meander for high packing density. Thefunctional blocks described above may be included in the designdiscreetly, monolithically or in a hybrid package.

The depletion mode transistor in the functioning blocks described may bea Schottky gate HEMT described in prior art.

Additionally, the normally on (depletion mode) transistor in thefunctioning blocks described may be the pGaN islands transistordescribed above.

It will be appreciated that, as already mentioned, the auxiliaryheterojunction transistor may have the source and drain interchanged.Unlike in the active (high voltage) transistor, the source and drain inthe auxiliary heterojunction may be symmetrical or made and arranged ina similar way, so that the source can take the role of the drain andvice-versa.

According to a second aspect of the present disclosure, there isprovided a Gallium Nitride (GaN) chip comprising a III-nitridesemiconductor based heterojunction power device as according to theprevious aspect, and an auxiliary low-voltage transistor as according tothe previous aspect but wherein the auxiliary gate region terminal isoperatively connected to a current control circuit (block) and apull-down circuit (block). The current control block may be connectedbetween the first additional terminal and the auxiliary gate region. Thepull-down circuit block may be connected between the auxiliary gateterminal and the first terminal (source) of heterojunction power device(which is the same as the low voltage terminal of the GaN chip). Acircuit comprising at least an auxiliary low-voltage transistor, currentcontrol circuit (block) and pull-down circuit (block) may be referred toas a gate interface circuit.

The GaN chip may further comprise an over-current protection circuit asdescribed above where the low voltage transistor is in parallel with thepull-down circuit.

The GaN chip may further comprise an integrated current control circuit(block). As described above, the current control block provides thecurrent to charge and discharge the gate of the auxiliary HEMT in theauxiliary gate circuit. The current control block may be connectedbetween the first additional terminal and the gate of the auxiliaryHEMT.

In some embodiments, the integrated current control block may be aresistive element. This resistive element can be made using metal layersor the 2DEG layer.

In other embodiments the current control block may be or comprise acurrent source. The current source may be composed of a low-voltagedepletion mode HEMT and a resistive element. The drain of thelow-voltage HEMT may be connected to the first additional terminal, thesource to the first terminal of the resistive element and the gate tothe second terminal of the resistive element. The second terminal of theresistive element may be further connected to the gate terminal of theauxiliary HEMT.

In similar embodiments, an RCL network could be included in parallel orin series with the resistive element or the current source to improvethe characteristics of the current control block.

The current control block may further include a circuit creating anadditional voltage drop. Such circuit could be one or severallow-voltage diodes, one or several low-voltage HEMT with gate connectedto source or a low-voltage enhancement mode HEMT with a potentialdivider connected between the drain and source terminal of the HEMTwhere the midpoint of the potential divider is connected to the gateterminal of the HEMT.

In a further embodiment of the current control block, the voltage dropin the current block may be created using a similar circuit as the oneused to create a voltage drop between the external gate of the GaN chip(also described as control terminal) and the gate of the active GaN HEMT(also described as the power transistor or high voltage transistor).This circuit, referred to as a gate interface circuit above, has beendescribed as comprising an auxiliary transistor, a current controlcircuit and a pull-down circuit. Such a circuit (and any otherembodiments described herein) could be implemented within the currentcontrol block to provide the additional voltage drop described. Further,the current control block may be connected to an additional separateinternal or external control signal.

In one embodiment of the current control block connected to an internalcontrol signal, the current control block may be connected to the outputof a buffer, single-stage or multi-stage inverter or transistor switch.

In any embodiment, one or several current control blocks may be used.

The current control block may further include a circuit that adapts thecurrent in the current control block. Such a current reduction circuitmay include a depletion mode HEMT or enhancement mode HEMT in series orin parallel to the resistive element in the current source. The gate ofsaid HEMT may be connected to a voltage divider between the gate of theauxiliary HEMT and the first terminal or to a node within the integratedpull-down circuit.

Alternatively, the current control circuit may comprise at least one lowvoltage transistor (HEMT) having at least one terminal connected to aconstant or variably controlled voltage level. For example the gate ofsaid HEMT may be connected to a constant or variably controlled voltagelevel. This voltage level can be supplied from an on-chip circuit (suchas a regulator or start-up), an external source or a combination of thetwo. As either the electric potential of said voltage level or thepotential of the source of said HEMT changes the current level in thecurrent source changes.

Further, said HEMT may be connected in parallel to the current controlblock.

The heterojunction GaN chip may further comprise an integrated pull-downcircuit block. The pull-down circuit block may be connected between thegate of the auxiliary HEMT and the first terminal (source terminal ofthe main power heterojunction transistor—the same as the low-voltageterminal of the GaN chip).

In some embodiments, the integrated pull-down circuit block can be oneor several normally-on or normally-off HEMTs in parallel or in series.There may be additional capacitors or resistors in series with theHEMTs. The gate potentials of said pull-down HEMTs are controlled to setthe voltage drop across the pull-down HEMT and therefore setting thegate voltage of the auxiliary gate block and the voltage drop across theauxiliary gate block.

In one embodiment, the gate terminal of the pull-down HEMT may beconnected to the output of a voltage divider between the gate terminalof the auxiliary HEMT and the first terminal.

In another embodiment, the gate terminal of the pull-down HEMT may beconnected to the output of a voltage (or potential) divider between thesource terminal of the HEMT in the current source of the current controlblock and the first terminal.

In a further embodiment, the gate terminal of the pull-down HEMT may beconnected to the output of a voltage divider between the active gate andthe first terminal.

In a fourth embodiment, the gate terminal of the pull-down HEMT may beconnected to the output of a voltage divider between the firstadditional terminal and the first terminal.

In a further embodiment, an additional current control block isconnected to the first additional terminal. This additional currentcontrol block is connected to an additional pulldown circuit which isconnected to the first terminal. In this embodiment, the gate terminalof the first pull-down HEMT may be connected to the output of a voltagedivider across the additional pull-down circuit.

In all these embodiments of a pull-down circuit, a voltage divider mayconsist of resistive elements such as resistors formed of metal or 2DEG;capacitors; current sources formed of a depletion-mode HEMT and with thesource connected to the first terminal of a resistive element and thegate connected to the second terminal; Schottky diodes, enhancement modeHEMTs with the gate terminal connected to their source terminal; HEMTswith the gate terminal connected to the output of a voltage dividerbetween their drain and source; or similar voltage divider circuits.

The pull-down circuit or the current control or the auxiliary gatecircuit may further comprise an element to compensate or reduce theeffect of temperature. This element is a particular embodiment of thevoltage divider which is part of the pull-down circuit. The first partof the voltage divider may comprise an integrated resistor and thesecond part of the voltage divider may comprise a current sourceconsisting of a normally-on HEMT with the source connected to the firstterminal of an additional resistor and the gate connected to the secondterminal of the resistor. The first part of the voltage divider mayfurther comprise a similar current source in parallel to the resistor.The second part of the voltage divider may further comprise a resistorin parallel to the current source.

Both parts of the voltage divider will increase the voltage drop at agiven current with increasing temperature. But the current sources andresistors change the voltage drop at a dissimilar rate. By designing thesizes of the normally-on HEMTs and the resistances, the output of thevoltage divider can be set by the design in such a way that the voltagedrop across the pull-down circuit and/or the voltage drop across theauxiliary HEMT has a much smaller temperature dependence.

In a further embodiment, the gate of the pull down HEMT is controlled byan over current protection or over temperature protection circuit.

In a further embodiment, the gate of the pull down HEMT is controlleddirectly or indirectly by an external circuit or by an additionalcircuit integrated on the GaN devices.

The GaN chip may incorporate more than one main power device. Forexample half bridge configurations where the low-side power device isconnected in series with a high-side main power device are possible.Full bridge consisting of two arms of half bridges or a three phase GaNchip configuration are also possible. According to this aspect of theinvention at least one main power device in these configurations(half-bridge or full bridge or three phase) comprises an auxiliary gatecircuit, a pull-down circuit and a current control-circuit as describedabove.

In an arrangement where more than one main power device is used (such aswhen parallel main power transistors are used), the described blockssuch as auxiliary gate circuit, pull-down circuit and currentcontrol-circuit or parts thereof may be shared among the several mainpower devices to achieve more compact solutions. For example, DC voltagerails or disable signal can be shared in this way to avoid duplicationand save area.

The heterojunction chip (GaN chip) may further comprise a shieldingand/or decoupling structure disposed between any two or more of: the atleast one main power heterojunction transistor; the auxiliary gatecircuit; the pull-down circuit; and/or the current control circuit(block).

The shielding and/or decoupling structure may comprise any of: one ormore layers of two-dimensional carrier gas of the first and/or secondconductivity type; one or more metal layers; and/or one or moreconductive layers; and the shielding and/or decoupling structure may beoperatively connected to one of: the first terminal; a potential; orground.

The heterojunction chip may further comprise measures to reduce unwantedelectrical coupling or electrical interference between the activeheterojunction power transistor (active GaN device or main power HEMT)and any of the auxiliary heterojunction transistors (auxiliary gatestructures) as well as between elements of the circuits of the auxiliaryheterojunction transistors (auxiliary gate structures). Suchinterference can be in the form of leakage currents, displacementcurrents, capacitive or inductive coupling from the active GaN device tothe auxiliary gate structure.

According to this disclosure there may be provided shielding and/ordecoupling structure(s) to eliminate or reduce such electricalinterference.

The shielding and/or decoupling structures may comprise one or morelayers of two-dimensional carrier gas of the first and/or secondconductivity type; one or more metal layers; and/or one or moreconductive layers between the active heterojunction power transistor(active GaN device) and the auxiliary heterojunction transistor(auxiliary structures). The shielding and/or decoupling structures maybe connected to the first terminal or any other suitable electricalpotential (such as ground). The shielding and/or decoupling structuresmay be placed around, below, above, on the sides and/or in the vicinityof any of the auxiliary heterojunction transistors (auxiliary gatestructures) or the active heterojunction power transistor (GaN activedevice).

Said conductive layers may comprise two-dimensional carrier gases (e.g.2DEG), metals, poly-silicon, Ill-nitride semiconductors, othersemiconductors or any other conductive materials. In an example, theheterojunction chip may comprise a 2DEG structure operatively connectedto the first terminal and placed at least partially around the auxiliaryGaN structure. In this example the 2DEG is connected to an appropriatepotential (e.g. ground) in order to reduce the resistive and capacitivecoupling from the active GaN HEMT through the substrate or III-nitridesemiconductor region to the auxiliary gate structure or circuitry.

Shielded structures may be capacitors, resistors, HEMTs or any otheractive and passive devices on the chip.

The shielding and/or decoupling structures may be formed between anyblocks of the circuit to isolate the respective blocks from theinfluence of each other.

In a further embodiment, the pull-down circuit may comprise of a voltagesource in series with one or more enhancement HEMTs with their gateterminal connected to their source terminal. The voltage source may bethe output of an on-chip or external voltage regulator. The voltagesource can be constant or variably controlled. This circuit block can beplaced in parallel to any other pull-down circuit block to make theoverall function of the pull-down more effective.

Alternatively, the pull-down circuit may comprise a voltage source inseries with one or more enhancement HEMTs in a threshold multiplierarrangement or any other circuit with a diode-like characteristic;wherein the voltage source is configured to be constant or variable;and, optionally wherein the voltage source is connected to an on-chip orexternal voltage regulator. In some implementations, the pull-downcircuit may comprise an active transistor switch instead of the one ormore enhancement HEMTs with a gate terminal connected to the sourceterminal.

According to a further aspect of the present disclosure, there isprovided A method of manufacturing a III-nitride semiconductor basedheterojunction power device, the method comprising:

-   -   forming an active heterojunction power transistor on a        substrate, the active heterojunction transistor comprising:        -   a first III-nitride semiconductor region comprising a first            heterojunction comprising an active two dimensional carrier            gas;        -   a first terminal operatively connected to the III-nitride            semiconductor region;        -   a second terminal laterally spaced from the first terminal            and operatively connected to the III-nitride semiconductor            region;        -   an active gate region formed over the III-nitride            semiconductor region, the active gate region being formed            between the first terminal and the second terminal;    -   forming a first auxiliary heterojunction transistor on the        substrate or on a further substrate, the auxiliary        heterojunction transistor comprising:        -   a second III-nitride semiconductor region comprising a            second heterojunction comprising an auxiliary two            dimensional carrier gas;        -   a first additional terminal operatively connected to the            second III-nitride semiconductor region;        -   a second additional terminal laterally spaced from the first            additional terminal and operatively connected to the second            III-nitride semiconductor region;        -   an auxiliary gate region formed over the second III-nitride            semiconductor region, the auxiliary gate region being formed            between the first additional terminal and the second            additional terminal;    -   forming a second auxiliary heterojunction transistor on the        substrate or the further substrate,    -   operatively connecting the first additional terminal with the        auxiliary gate region, and    -   operatively connecting the second additional terminal with the        active gate region,    -   operatively connecting the second auxiliary heterojunction        transistor in parallel with the first auxiliary transistor,    -   operatively connecting the first additional terminal of the        first auxiliary heterojunction transistor to a source terminal        of the second auxiliary heterojunction transistor, and    -   operatively connecting the second additional terminal of the        first auxiliary heterojunction transistor to a drain terminal of        the second auxiliary heterojunction transistor.

The method may further comprise forming an isolator region between theactive heterojunction transistor and auxiliary heterojunction transistorseparating the active two dimensional carrier gas and the auxiliary twodimensional carrier gas.

The method may further comprise forming the first III-nitridesemiconductor region at the same time as forming the second III-nitridesemiconductor region.

The method may further comprise forming the active gate region at thesame time as forming the auxiliary gate region.

The method may further comprise forming a metallization layer for thefirst terminal, the second terminal, the first additional terminal, andthe second additional terminal at the same time.

The method may further comprise measures to reduce unwanted electricalcoupling or electrical interference between the active heterojunctionpower transistor (active GaN device or main power HEMT) and any of theauxiliary heterojunction transistors (auxiliary gate structures) as wellas between elements of the circuits of the auxiliary heterojunctiontransistors (auxiliary gate structures). Such interference can be in theform of leakage currents, displacement currents, capacitive or inductivecoupling from the active GaN device to the auxiliary gate structure.

According to this disclosure there may be provided shielding and/ordecoupling structure(s) to eliminate or reduce such electricalinterference.

The method of manufacturing a III-nitride semiconductor-basedheterojunction power device may further comprise forming shieldingand/or decoupling structures. Forming shielding and/or decouplingstructures may comprise connecting one or more layers of two-dimensionalcarrier gas of the first and/or second conductivity type; one or moremetal layers; and/or one or more conductive layers between the activeheterojunction power transistor (active GaN device) and any of theauxiliary heterojunction transistors (auxiliary structures). Theshielding and/or decoupling structures may be connected to the firstterminal or any other suitable electrical potential (such as ground).The shielding and/or decoupling structures may be placed around, below,above, on the sides and/or in the vicinity of any of the auxiliaryheterojunction transistors (auxiliary gate structures) or the activeheterojunction power transistor (GaN active device).

Said conductive layers may comprise two-dimensional carrier gases (e.g.2DEG), metals, poly-silicon, Ill-nitride semiconductors, othersemiconductors or any other conductive materials. In an example, themethod may comprise forming a 2DEG structure operatively connected tothe first terminal and placed at least partially around the auxiliaryGaN structure. In this example the 2DEG is connected to an appropriatepotential (e.g. ground) in order to reduce the resistive and capacitivecoupling from the active GaN HEMT through the substrate or III-nitridesemiconductor region to the auxiliary gate structure or circuitry.

Shielded structures may be capacitors, resistors, HEMTs or any otheractive and passive devices on the chip.

The shielding and/or decoupling structures may be formed between anyblocks of the circuit to isolate the respective blocks from theinfluence of each other.

BRIEF DESCRIPTION OF THE PREFERRED EMBODIMENTS

The present disclosure will be understood more fully from the detaileddescription that follows and from the accompanying drawings, whichhowever, should not be taken to limit the disclosure to the specificembodiments shown, but are for explanation and understanding only.

FIG. 1 shows schematically the cross section in the active area of aprior art pGaN HEMT;

FIG. 2 illustrates a schematic representation of a cross section of theactive area of the proposed disclosure according to one embodiment ofthe disclosure;

FIG. 3 shows a circuit schematic representation of one embodiment of theproposed disclosure as shown in the schematic cross section of FIG. 2;

FIG. 4A shows a circuit schematic representation of a further embodimentof the proposed disclosure in which a low on-state voltage diode isconnected in parallel between the drain and the source of the auxiliarytransistor;

FIG. 4B illustrates a 3D schematic representation of the embodiment ofFIG. 4A;

FIG. 4C shows the cross section of the low voltage diode as used inembodiment of FIG. 4A;

FIG. 5 shows a circuit schematic representation of a further embodimentof the proposed disclosure in which the drain (gate) terminal and thesource terminal of the auxiliary transistor are available as externalgate terminals;

FIG. 6 shows a circuit schematic representation of a further embodimentof the proposed disclosure where a second auxiliary transistor isconnected in parallel with a first auxiliary transistor where the drain(gate) terminal of the first low auxiliary transistor is connected tothe source terminal of the second auxiliary transistor and the sourceterminal of the first auxiliary transistor is connected to the drain(gate) terminal of the second auxiliary transistor;

FIG. 7 shows a circuit schematic representation of a further embodimentof the proposed disclosure where a resistor is added between the drainterminal and gate terminal of the second auxiliary transistor;

FIG. 8 shows a circuit schematic representation of a further embodimentof the proposed disclosure where an additional resistor is added betweenthe source terminal of the auxiliary transistor (drain terminal of thesecond auxiliary transistor) and source terminal of the active device;

FIG. 9 shows a circuit schematic representation of a further embodimentof the proposed disclosure where a third auxiliary transistor is addedbetween the drain terminal and gate terminal of the second auxiliarytransistor. The gate terminal of the third auxiliary transistor isconnected to the source terminal of the third auxiliary transistor;

FIG. 10 shows a circuit schematic representation of a further embodimentof the proposed disclosure where a third auxiliary transistor is addedbetween the drain terminal and gate terminal of the second auxiliarytransistor. The gate terminal of the third auxiliary transistor isconnected to the drain terminal of the third auxiliary transistor;

FIG. 11 shows a circuit schematic representation of a further embodimentof the proposed disclosure where a voltage limiting circuit isimplemented composed of two resistors forming a potential divider and anactively switched low voltage enhancement mode transistor;

FIG. 12 shows a circuit schematic representation of a further embodimentof the proposed disclosure where a voltage limiting circuit isimplemented composed of two resistors forming a potential divider and anactively switched low voltage depletion mode transistor;

FIG. 13 shows a circuit schematic representation of a further embodimentof the proposed disclosure where an over-current protection circuit isimplemented composed of a resistor and an actively switched low voltageenhancement mode transistor;

FIG. 14 shows a circuit schematic representation of a further embodimentof the proposed disclosure where an over-current protection circuit isimplemented composed of a resistor and an actively switched low voltagedepletion mode transistor;

FIG. 15 shows a circuit schematic representation of a further embodimentof the proposed disclosure where an active Miller clamp circuit isimplemented composed of a resistor, an actively switched low voltageenhancement mode transistor and an actively switched depletion modetransistor;

FIG. 16 shows a circuit schematic representation of a further embodimentof the proposed disclosure where an active Miller clamp circuit isimplemented composed of a resistor, an actively switched low voltageenhancement mode transistor and an actively switched enhancement modetransistor;

FIG. 17 illustrates a schematic representation of a cross section of theactive area of a proposed depletion mode device in prior art which canbe used as an actively switched transistor;

FIG. 18 illustrates a three dimensional schematic representation of theactive area of a proposed depletion mode device with pGaN islands (notfound in prior art) which can be used as an actively switchedtransistor;

FIG. 19 illustrates a three dimensional schematic representation of theactive area of the depletion mode device with pGaN islands shown in FIG.18 operated in diode mode; and

FIG. 20 shows the transfer characteristic of the proposed depletion modedevice shown in FIG. 18.

FIG. 21 illustrates a schematic representation of a cross-section of theactive area of the proposed disclosure according to another embodimentof the disclosure. In this embodiment, the first additional terminal 16and the auxiliary gate terminal 15 are not operatively connected.

FIG. 22 shows a circuit schematic representation of one embodiment ofthe proposed disclosure as shown in the schematic cross-section of FIG.21.

FIG. 23 shows a schematic representation of the second aspect of the oneembodiment of the proposed disclosure where the gate terminal of theauxiliary gate block is controlled by a current control block and apull-down circuit block.

FIG. 24 shows the relationship between the external gate voltage biasand the active gate voltage.

FIG. 25 shows a circuit schematic representation of a further embodimentof the proposed disclosure where the current control block consists of aresistive element and the pull-down circuit comprises a HEMT inthreshold multiplier configuration.

FIG. 26 shows a circuit schematic representation of a further embodimentof the proposed disclosure where the current control block comprises aresistive element with resistive and capacitive elements in parallel andwhere the pull-down circuit comprises a HEMT in threshold multiplierconfiguration, with additional capacitive elements.

FIG. 27 shows a circuit schematic representation of a further embodimentof the proposed disclosure where the current control block comprises anormally-on HEMT and a resistive element in series where the gate of thenormally-on HEMT is connected to the second terminal of the resistiveelement; and where the pull-down circuit comprises a HEMT in thresholdmultiplier configuration. In this embodiment, the auxiliary gate blockcomprises an enhancement mode low voltage HEMT and a Schottky diode inparallel.

FIG. 28 shows a circuit schematic representation of a further embodimentof the proposed disclosure where the current control block comprises anormally-on HEMT and a resistive element in series where the gate of thenormally-on HEMT is connected to the second terminal of the resistiveelement; and where the pull-down circuit comprises a HEMT in thresholdmultiplier configuration.

FIG. 29 shows a circuit schematic representation of a further embodimentof the proposed disclosure where the auxiliary gate block comprises asecond auxiliary transistor connected in parallel with a first auxiliarytransistor where the gate terminal of the second auxiliary transistor isconnected to the source terminal of the first auxiliary transistor;

FIG. 30 shows a circuit schematic representation of a further embodimentof the proposed disclosure where the pull-down circuit comprises a HEMTin threshold multiplier configuration. In this embodiment, the voltagedivider of the pull-down circuit comprises a temperature compensationcircuit comprising a current source in parallel with a resistiveelement.

FIG. 31 shows a circuit schematic representation of a further embodimentof the proposed disclosure where the voltage divider of the pull-downcircuit is connected to the source terminal of the HEMT of the currentcontrol block.

FIG. 32 shows a schematic representation of one embodiment of theproposed disclosure where the gate terminal of the auxiliary gate blockis controlled by a current control block and a pull-down circuit block;and where the Miller clamp HEMT is controlled by a logic inverter. Thelogic inverter is supplied by the output voltage of an integrated DC/DCvoltage regulator. Further, the input of the logic inverter is theoutput of a VG to Vlogic voltage regulator, limiting the voltage fromthe first additional terminal to a level that is optimised for theintegrated GaN HEMT included in the inverter circuit.

FIG. 33 shows a circuit schematic representation of a further embodimentof the proposed disclosure where the auxiliary gate block comprises anormally-on HEMT.

FIG. 34 shows a circuit schematic representation of a further embodimentof the proposed disclosure where the auxiliary gate block comprises anormally-on HEMT and where the auxiliary gate block comprises a secondauxiliary transistor connected in parallel with a first auxiliarytransistor where the gate terminal of the second auxiliary transistor isconnected to the source terminal of the first auxiliary transistor;

FIG. 35 shows a circuit schematic representation of a further embodimentof the proposed disclosure where the auxiliary gate block comprises anormally-on HEMT and where the auxiliary gate block comprises a secondauxiliary normally-on HEMT connected in parallel with a first auxiliarytransistor where the gate terminal of the second auxiliary transistor isconnected to the first terminal;

FIG. 36 shows a circuit schematic representation of a further embodimentof the proposed disclosure where the voltage divider of the pull-downcircuit is connected to the active gate terminal.

FIG. 37 shows a circuit schematic representation of a further embodimentof the proposed disclosure where the voltage divider of the pull-downcircuit is connected to the active gate terminal and where the voltagedivider comprises a series of source-gate connected E-HEMTs.

FIG. 38 shows a circuit schematic representation of a further embodimentof the proposed disclosure where the voltage divider of the pull-downcircuit is connected to the active gate terminal and where the voltagedivider comprises a HEMT in a threshold multiplier configuration.

FIG. 39 shows a circuit schematic representation of a further embodimentof the proposed disclosure where the voltage divider of the pull-downcircuit is connected to the first additional terminal and where thevoltage divider comprises a HEMT in a threshold multiplierconfiguration.

FIG. 40 shows a circuit schematic representation of a further embodimentof the proposed disclosure where the voltage divider of the pull-downcircuit is connected to the first additional terminal and where thevoltage divider comprises a current source, formed of a normally-on HEMTand a resistor, and a HEMT in a threshold multiplier configuration. Inthis embodiment, the output of the voltage divider is the gate terminalof the HEMT which is in threshold multiplier configuration.

FIG. 41 illustrates an interdigitated device layout of a furtherembodiment of the disclosure incorporating an auxiliary gate structurewith the current control block and the pull-down circuit block.

FIG. 42 illustrates an interdigitated device layout of a furtherembodiment of the disclosure in which the auxiliary gate with thecurrent control block and the pull-down circuit block and terminalregions are placed below the source pad metal.

FIG. 43 shows a block diagram of a further embodiment of the proposeddisclosure where any of the embodiments of the GaN chip power deviceaccording to this disclosure are placed in a half-bridge configuration.

FIG. 44 shows a block diagram of a further embodiment of the proposeddisclosure where any of the embodiments of the GaN chip power deviceaccording to this disclosure are placed in a three-phase half-bridgeconfiguration.

FIG. 45 shows a schematic representation of one embodiment of ashielding and decoupling structure between two structures of the chip.In this embodiment, the decoupling structures consist of 2DEG structuresohmic contacts and connections to metal layers through vias. The metallayer may be shaped similar to the 2DEG.

FIG. 46 shows a schematic representation of one embodiment of theinvention in which the pull-down circuit comprises an additional voltageinput from an external terminal.

FIG. 47 shows a schematic representation of one embodiment of theinvention in which the pull-down circuit comprises an additional voltageinput stemming from a voltage source on the chip. This voltage sourcemay be the output of a voltage regulator, voltage divider, charge pumpor other switched voltage converter.

FIG. 48 shows a schematic representation of one embodiment of thepull-down circuit comprising a voltage source and capacitor in serieswith an enhancement HEMT with the gate terminal connected to the sourceterminal.

FIG. 49 shows a schematic representation of one embodiment of thepull-down circuit comprising a voltage source and capacitor in serieswith an enhancement HEMT in a threshold multiplier configuration.

FIG. 50 shows a block diagram of a voltage regulator connected to theinput of the receiving circuit (for example logic inverter) through adecoupling circuit. The decoupling circuit reduces or eliminates theimpact of voltage excursions or current spikes from the voltage sourceto the receiving circuit.

FIG. 51 shows a schematic circuit of a decoupling circuit comprising aresistive element and a capacitive element.

FIG. 52 shows a schematic circuit of a decoupling circuit comprising acurrent source and a capacitive element. The current source comprises adepletion HEMT and a resistive element.

FIG. 53 shows a schematic circuit of a decoupling circuit comprising acurrent source and a capacitive element. The current source comprises adepletion HEMT and a resistive element. In this embodiment, anadditional HEMT in parallel to the current source allows the adjustmentof the current limit.

FIG. 54 shows a schematic circuit of a decoupling circuit comprising acurrent source and a capacitive element. The current source comprises adepletion HEMT and a resistive element. In this embodiment, anadditional HEMT in parallel to the resistive element allows theadjustment of the current limit.

FIG. 55 shows a schematic circuit of a decoupling circuit comprising acurrent source and a capacitive element. The current source comprises adepletion HEMT and a resistive element. In this embodiment, anadditional HEMT in parallel to the capacitive element allows sinking thecurrent in case of a current spike. The additional HEMT is turned on bya resistive and capacitive voltage divider on the input side of thedecoupling circuit.

FIG. 56 shows an embodiment of FIG. 55 in which the additional HEMT inparallel with the current source is controlled by having its gateconnected to the gate voltage of the active HEMT. In this embodiment,the coupling is strong when the active HEMT is in the on-state, weakwhen the active HEMT is off.

FIG. 57 shows a schematic of an embodiment of the current control blockwith an enhancement HEMT in parallel to the resistive element with thegate connected to a DC voltage level. As the voltage level of the sourceof the HEMT rises the resistance is increased and the current isreduced.

FIG. 58 shows a schematic of an embodiment of the current control blockwith a depletion HEMT in parallel to the resistive element with the gateconnected to a DC voltage level. As the voltage level of the source ofthe HEMT rises the resistance is increased and the current is reduced.

FIG. 59 shows a schematic representation of one embodiment of a D-HEMTwith p-GaN islands arranged in two rows operatively connected to thegate contact. The p-GaN islands form a meander shape between them.

FIG. 60 shows a schematic representation of one embodiment of a D-HEMTwith p-GaN islands arranged in three rows operatively connected to thegate contact. The p-GaN islands form a labyrinth shape between them.

FIG. 61 shows a logic inverter circuit with an enhancement transistor onthe low side and a resistive element as a pull-up circuit.

FIG. 62 shows a logic inverter circuit with an enhancement transistor onthe low side and a current source as a pull-up circuit. The currentsource comprises a depletion transistor and a resistive element inseries.

FIG. 63 shows a two-stage logic inverter circuit. Each stage has anenhancement transistor on the low side with the gate connected to theinput signal. The pull up circuit of the first stage is a currentsource, as shown above. The pull-up circuit of the second stagecomprises a depletion transistor and a resistive element in series,where the gate of the depletion transistor is connected to the output ofthe first stage.

FIG. 64 shows a two-stage logic inverter circuit. Compared to thecircuit in FIG. 63, an additional enhancement transistor is added to thepull-up circuit of the second stage in parallel to the resistiveelement.

FIG. 65 shows a two-stage logic inverter circuit. Compared to thecircuit in FIG. 63, an additional transistor is added to the pull-upcircuit of the second stage in parallel to the series arrangement withthe depletion transistor and resistive element.

FIG. 66 shows a schematic representation of an embodiment of theinvention with the current control block connected to a separate controlterminal. Further, an enable and disable function is connected acrossthe pull-down circuit. The enable and disable function comprises a logicinverter and an enhancement HEMT connected between the source of theactive HEMT and the gate of the auxiliary HEMT.

FIG. 67 shows a schematic representation of an embodiment of theinvention with an actively controlled current control block. In thisembodiment, the current control block comprises a resistive element thatis connected to the output of a transistor switch controlled by a bufferfrom a control signal. Further, an enable and disable function isconnected across the pull-down circuit. The enable and disable functioncomprises a logic inverter and an enhancement HEMT connected between thesource of the active HEMT and the gate of the auxiliary HEMT.

FIG. 68 shows a schematic representation of an embodiment of theinvention with an actively controlled current control block, a voltageregulator between the control terminal and the current control block.Further, it comprises an enable and disable function connected to thegate of the auxiliary HEMT.

FIG. 69 shows a schematic representation of several exemplaryembodiments of disable or enable functions. The disable or enablefunction may be integrated with the gate of the active HEMT, with theMiller clamp transistor, with the inverter circuit or with the pull-downcircuit.

FIG. 70 shows a schematic representation of an arrangement with morethan one main power device sharing the source. One or several inputsignals or input DC voltages may be shared between several gateinterfaces. One or several signals or DC voltages generated in one gateinterface circuit may be used in other gate interface circuits.

FIG. 71 shows an example of a current-voltage characteristic of theD-HEMT transistor illustrated in FIGS. 59 and 60.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 2 illustrates a schematic representation of a cross section of theactive area of the proposed disclosure, according to one embodiment ofthe disclosure. In use the current flows in the active area of thesemiconductor device. In this embodiment, the device comprises asemiconductor (e.g. silicon) substrate 4 defining a major (horizontal)surface at the bottom of the device. Below the substrate 4 there is asubstrate terminal 5. The device includes a first region of a transitionlayer 3 on top of the semiconductor substrate 4. The transition layer 3comprises a combination of III-V semiconductor materials acting as anintermediate step to allow the subsequent growth of regions of highquality III-V semiconductor materials.

On top of the transition layer 3 there exists a second region 2. Thissecond region 2 is of high quality III-V semiconductor (for example GaN)and comprises several layers. A third region 1 of III-V semiconductorcontaining a mole fraction of Aluminium is formed on top of the secondregion 2. The third region 1 is formed such that a hetero-structure isformed at the interface between the second 2 and third region 1resulting in the formation of a two dimensional electron gas (2DEG).

A fourth region of highly p-doped III-V semiconductor 11 is formed incontact with the third region 1. This has the function of reducing the2DEG carrier concentration when the device is unbiased, and is pGaNmaterial in this embodiment. A gate control terminal 10 is configuredover the fourth region 11 in order to control the carrier density of the2DEG at the interface of the second 2 and third region 1. A high voltagedrain terminal 9 is arranged in physical contact with the third region1. The high voltage drain terminal forms an ohmic contact to the 2DEG. Alow voltage source terminal 8 is also arranged in physical contact withthe third region 1 and also forms an ohmic contact to the 2DEG.

A portion of surface passivation dielectric 7 is formed on top of thefourth region 1 and between the drain terminal 9 and source terminal 8.A layer of SiO₂ passivation 6 is formed above the surface passivationdielectric 7 and source and drain terminals 8, 9.

The device is separated into two cross sections by a vertical cutline.The two cross sections may not be necessarily placed in the same plane.The features described above are on one side (right hand side, forexample) of the vertical cutline. This is termed as the active device205. The other side of the vertical cutline (the left hand side, forexample) is termed as the auxiliary device 210, which also comprises asemiconductor substrate 4, a transition layer 3, a second region 2 and aSiO₂ passivation region 6.

A fifth region of III-V semiconductor 17 containing a mole fraction ofAluminium is positioned above the second region 2 in the auxiliarydevice such that a hetero-structure is formed at the interface betweenthis fifth region 17 and the second region 2. This results in theformation of a second two dimensional electron gas (2DEG) in a regionwhich will be referred to as the auxiliary gate. This AlGaN layer 17 ofthe auxiliary device 210 can be identical or different to the AlGaNlayer 1 in the active device 205. The AlGaN layer thickness and Al molefraction are critical parameters as they affect the carrier density ofelectrons in the 2DEG [15].

A sixth region of highly p-doped III-V semiconductor 14 is formed on topof and in contact with the fifth region 17. This has the function ofreducing the 2DEG carrier concentration when the auxiliary gate isunbiased. An auxiliary gate control terminal 15 is configured over thesixth region 14 in order to control the carrier density of the 2DEG atthe interface of the fifth 17 and second region 2. The auxiliary gatepGaN layer 14 may be identical or different to the active gate pGaNlayer 11. Critical parameters which could differ include, but are notlimited to, pGaN doping and width along the x-axis (shown in thefigure).

An isolation region 13 is formed down the vertical cutline. This cutsthe electrical connection between the 2DEG formed in the active device205 and the 2DEG formed in the auxiliary device 210.

A first additional terminal 16 is arranged on top of and in physicalcontact with the fifth region 17 of the auxiliary device 210. This formsan ohmic contact to the 2DEG of the auxiliary device 210 and is alsoelectrically connected (via interconnection metal) to the auxiliary gatecontrol terminal 15 configured over the sixth region (pGaN) 14. Thefirst additional terminal 16 is biased at the same potential as theauxiliary gate terminal 15 of the auxiliary device. A second additionalterminal 12 is also arranged on top of and in physical contact with thefifth region 17 of the auxiliary device 210. This forms an ohmic contactto the 2DEG of the auxiliary device 210 and is electrically connected(via interconnection metal) to the active gate control terminal 10configured over the fourth region 11 of the active device 205. Theinterconnection between the second additional terminal 12 of theauxiliary device 210 and the active gate terminal 10 of the activedevice 205 can be made in the third dimension and can use differentmetal layers in the process. Note that this interconnection is not shownin the schematic in FIG. 2. A similar but not necessarily identicalAlGaN/GaN structure is used in the auxiliary gate.

When the device is in use the auxiliary gate 14, 15 drives the activegate 10, 11. The auxiliary 2DEG layer formed between the first andsecond additional terminals 12, 16 with the portion under the auxiliaryp-GaN gate 14 is controlled by the potential applied to the auxiliarygate terminal 15.

The portion of the auxiliary 2DEG under the auxiliary pGaN gate 14 isdepleted when the auxiliary gate terminal 15 and the short-circuitedfirst additional terminal 16 are at 0V. As the auxiliary gate bias isincreased (both terminals 15, 16) the 2DEG starts forming under the pGaNgate 14 connecting to the already formed 2DEG layer which connects tothe first and second additional terminals 16, 12. A 2DEG connection isnow in place between the first and second additional terminals 12, 16.

As the second additional terminal 12 is connected to the active gate 10the device can now turn on. A positive (and desirable) shift in thedevice threshold voltage is observed using this structure as not all ofthe potential applied to the auxiliary gate 15 is transferred to theactive gate 10. Part of this potential is used to form the auxiliary2DEG under the auxiliary gate 15 and only part is transferred to thesecond additional terminal 12 which is connected to the active gate 10.

The auxiliary gate provides the additional advantage of being able tocontrol the gate resistance of the device more easily. This can beachieved by varying the field plate design or distance between terminals12 and 15 or 15 and 16. This can be useful in controlling the unwantedoscillations observed due to the fast switching of these devices.

Different embodiments of the device can include terminals 10, 15 beingeither Schottky or Ohmic contacts or any combination of those two.

FIG. 3 shows a circuit schematic representation of one embodiment of theproposed disclosure as shown in the schematic cross section of FIG. 2.The features shown in FIG. 3 carry the same reference numbers as thefeatures in FIG. 2.

FIG. 4A shows a circuit schematic representation of a further embodimentof the proposed disclosure in which a low on-state voltage diode isconnected in parallel between the drain and the source of the auxiliarytransistor, as shown in the schematic 3D illustration in FIG. 4B. Manyof the features of this embodiment are similar to those of FIG. 2 andtherefore carry the same reference numerals, i.e., the semiconductorsubstrate 4, substrate terminal 5, transition layer 3, GaN layer 2,AlGaN layer 1, active pGaN layer 11, active gate terminal 10, surfacepassivation dielectric 7, low voltage source terminal 8, high voltagedrain terminal 9, SiO₂ passivation layer 6, isolation region 13,auxiliary AlGaN layer 17, auxiliary pGaN layer 14, auxiliary gate 15,first additional terminal 16 and second additional terminal 12. However,in this embodiment a low on-state voltage diode 31 is connected inparallel between the drain 16 and the source 12 of the auxiliarytransistor. The parallel diode 31 acts as pull-down network during theturn-off of the overall configuration connecting to ground the gateterminal 10 of the active GaN transistor. When a positive bias (known ason-state) is applied to the auxiliary gate 15, the diode 31 will bereverse-biased and zero current will flow through it, leaving unaffectedthe electrical behaviour of the overall high-voltage configuration. Whena zero bias (off-state) will be applied to the auxiliary gate 15 thediode 31 will be forward bias and the turn-off current flowing throughit will discharge the gate capacitance of the active transistor, thusenabling the switching off of the overall configuration. In off-state,the gate of the active device 10 will remain biased to a minimum voltageequal to the turn-on voltage of the diode. The diode 31 will thereforebe designed in such a way that its turn-on voltage will be as low aspossible, ideally few mV. FIG. 4B illustrates how the diode 31 could beincluded monolithically. The diode could be a simple Schottky diode orcould be a normal p-n diode. The diode 31 would pull down the activegate 10 during turn-off to the diode V_(th), therefore the diode needsto be designed to have as low a threshold voltage as possible. A featurewhich can achieve this is the use of a recessed anode such that thecontact is made directly to the 2DEG as seen in FIG. 4C.

FIG. 5 shows a circuit schematic representation of a further embodimentof the proposed disclosure in which the drain (gate) terminal 16 and thesource terminal 12 of the auxiliary transistor are available as externalgate terminals. Many of the features of this embodiment are similar tothose of FIG. 2 and therefore carry the same reference numerals, i.e.,the semiconductor substrate 4, substrate terminal 5, transition layer 3,GaN layer 2, AlGaN layer 1, active pGaN layer 11, active gate terminal10, surface passivation dielectric 7, low voltage source terminal 8,high voltage drain terminal 9, SiO₂ passivation layer 6, isolationregion 13, auxiliary AlGaN layer 17, auxiliary pGaN layer 14, auxiliarygate 15, first additional terminal 16 and second additional terminal 12.However, in this case the external gate terminal is divided into twoterminals. Since the gate driver sink output pin can now be connected tothe source terminal of the auxiliary transistor directly offering apull-down path, component 31 in FIG. 4 may (or may not) be omitted.

FIG. 6 shows a circuit schematic representation of a further embodimentof the proposed disclosure where a second auxiliary transistor 34 (couldbe advantageously low-voltage) is connected in parallel with the firstauxiliary transistor where the drain (gate) terminal 16 of the firstauxiliary transistor is connected to the source terminal of the secondauxiliary transistor and the source terminal 12 of the first auxiliarytransistor is connected to the drain (gate) terminal of the secondauxiliary transistor. Many of the features of this embodiment aresimilar to those of FIG. 2 and therefore carry the same referencenumerals, i.e., the semiconductor substrate 4, substrate terminal 5,transition layer 3, GaN layer 2, AlGaN layer 1, active pGaN layer 11,active gate terminal 10, surface passivation dielectric 7, low voltagesource terminal 8, high voltage drain terminal 9, SiO₂ passivation layer6, isolation region 13, auxiliary AlGaN layer 17, auxiliary pGaN layer14, auxiliary gate 15, first additional terminal 16 and secondadditional terminal 12. However, in this case the pull-down networkduring the turn-off of the overall configuration is a second auxiliarytransistor 34.

FIG. 7 shows a circuit schematic representation of a further embodimentof the proposed disclosure where a resistor 41 is added between thedrain terminal 12 and gate terminal 10 of the second auxiliarytransistor 34. Many of the features of this embodiment are similar tothose of FIG. 6 and therefore carry the same reference numerals, i.e.,the semiconductor substrate 4, substrate terminal 5, transition layer 3,GaN layer 2, AlGaN layer 1, active pGaN layer 11, active gate terminal10, surface passivation dielectric 7, low voltage source terminal 8,high voltage drain terminal 9, SiO₂ passivation layer 6, isolationregion 13, auxiliary AlGaN layer 17, auxiliary pGaN layer 14, auxiliarygate 15, first additional terminal 16, second additional terminal 12 andsecond auxiliary transistor 34. In this embodiment, the resistor 41 actsto reduce the active gate capacitance discharge time through thepull-down network during the turn-off of the active device. Theadditional resistor performs this function by creating an increasedpotential, during turn-off, of the second auxiliary transistor gateterminal 10 compared to the second auxiliary transistor drain terminal12.

FIG. 8 shows a circuit schematic representation of a further embodimentof the proposed disclosure where an additional resistor 42 is addedbetween the source terminal of the auxiliary transistor (drain terminal12 of the second auxiliary transistor) and source terminal 8 of theactive device. Many of the features of this embodiment are similar tothose of FIG. 7 and therefore carry the same reference numerals, i.e.,the semiconductor substrate 4, substrate terminal 5, transition layer 3,GaN layer 2, AlGaN layer 1, active pGaN layer 11, active gate terminal10, surface passivation dielectric 7, low voltage source terminal 8,high voltage drain terminal 9, SiO₂ passivation layer 6, isolationregion 13, auxiliary AlGaN layer 17, auxiliary pGaN layer 14, auxiliarygate 15, first additional terminal 16, second additional terminal 12,second auxiliary transistor 34 and resistive element 41. In thisembodiment, the additional resistive element 42 acts as an additionalpull-down network during the active device turn-off. During the activedevice turn-on and on-state the additional resistance 42 can act as avoltage limiting component to protect the gate terminal of the activedevice.

FIG. 9 shows a circuit schematic representation of a further embodimentof the proposed disclosure where a third auxiliary transistor 58 isadded between the drain terminal 12 and gate terminal 10 of the secondauxiliary transistor 34. Many of the features of this embodiment aresimilar to those of FIG. 8 and therefore carry the same referencenumerals, i.e., the semiconductor substrate 4, substrate terminal 5,transition layer 3, GaN layer 2, AlGaN layer 1, active pGaN layer 11,active gate terminal 10, surface passivation dielectric 7, low voltagesource terminal 8, high voltage drain terminal 9, SiO₂ passivation layer6, isolation region 13, auxiliary AlGaN layer 17, auxiliary pGaN layer14, auxiliary gate 15, first additional terminal 16, second additionalterminal 12, second auxiliary transistor 34 and additional resistiveelement 42. In this embodiment, the third auxiliary transistor acts toreduce the active gate capacitance discharge time through the pull-downnetwork during the turn-off of the heterojunction power device. Thethird auxiliary transistor 58 performs this function by creating anincreased potential, during turn-off, of the second auxiliary transistorgate terminal 10 compared to the second auxiliary transistor drainterminal 12. The third auxiliary transistor is a depletion mode device.The gate terminal of the third auxiliary transistor is connected to thesource terminal of the third auxiliary transistor.

FIG. 10 shows a circuit schematic representation of a further embodimentof the proposed disclosure where a third auxiliary transistor 59 isadded between the drain terminal 12 and gate terminal 10 of the secondauxiliary transistor 34. Many of the features of this embodiment aresimilar to those of FIG. 8 and therefore carry the same referencenumerals, i.e., the semiconductor substrate 4, substrate terminal 5,transition layer 3, GaN layer 2, AlGaN layer 1, active pGaN layer 11,active gate terminal 10, surface passivation dielectric 7, low voltagesource terminal 8, high voltage drain terminal 9, SiO₂ passivation layer6, isolation region 13, auxiliary AlGaN layer 17, auxiliary pGaN layer14, auxiliary gate 15, first additional terminal 16, second additionalterminal 12, second auxiliary transistor 34 and additional resistiveelement 42. In this embodiment, the third auxiliary transistor acts toreduce the active gate capacitance discharge time through the pull-downnetwork during the turn-off of the heterojunction power device. Thethird auxiliary transistor 59 performs this function by creating anincreased potential, during turn-off, of the second auxiliary transistorgate terminal 10 compared to the second auxiliary transistor drainterminal 12. The third auxiliary transistor is a depletion mode device.The gate terminal of the third auxiliary transistor is connected to thedrain terminal of the third auxiliary transistor.

FIG. 11 shows a circuit schematic representation of a further embodimentof the proposed disclosure where a voltage limiting circuit isimplemented composed of a resistor 44, a resistor 45 (forming apotential divider) and an actively switched low voltage enhancement modetransistor 43. Many of the features of this embodiment are similar tothose of FIG. 6 and therefore carry the same reference numerals, i.e.,the semiconductor substrate 4, substrate terminal 5, transition layer 3,GaN layer 2, AlGaN layer 1, active pGaN layer 11, active gate terminal10, surface passivation dielectric 7, low voltage source terminal 8,high voltage drain terminal 9, SiO₂ passivation layer 6, isolationregion 13, auxiliary AlGaN layer 17, auxiliary pGaN layer 14, auxiliarygate 15, first additional terminal 16, second additional terminal 12 andsecond auxiliary transistor 34. In this embodiment, the enhancement modetransistor 43 can turn-on, and thus adjust the resistance between theactive device gate terminal 10 and the active device source terminal 8,when the potential of the first additional terminal 16 (or the drain(gate) terminal 16) of the first auxiliary heterojunction transistor israised above a certain value which can be controlled by the choice ofresistors (44, 45) in the potential divider described. This function canprotect the active gate terminal from over-voltage events.

FIG. 12 shows a circuit schematic representation of a further embodimentof the proposed disclosure where a voltage limiting circuit isimplemented comprising a resistor 44, a resistor 45 (forming a potentialdivider) and an actively switched low voltage depletion mode transistor46. Many of the features of this embodiment are similar to those of FIG.6 and therefore carry the same reference numerals, i.e., thesemiconductor substrate 4, substrate terminal 5, transition layer 3, GaNlayer 2, AlGaN layer 1, active pGaN layer 11, active gate terminal 10,surface passivation dielectric 7, low voltage source terminal 8, highvoltage drain terminal 9, SiO₂ passivation layer 6, isolation region 13,auxiliary AlGaN layer 17, auxiliary pGaN layer 14, auxiliary gate 15,first additional terminal 16, second additional terminal 12 and secondauxiliary transistor 34. In this embodiment, the resistance of thedepletion mode transistor 46 can be reduced, and thus adjust theresistance between the active device gate terminal 10 and the activedevice source terminal 8, when the potential of the first additionalterminal 16 (or the drain (gate) terminal 16) of the first auxiliaryheterojunction transistor is increased. The potential divider formed bythe two resistors (44, 45) determines the potential on the gate terminalof the depletion mode transistor 46. The circuit described can protectthe active gate terminal from over-voltage events.

FIG. 13 shows a circuit schematic representation of a further embodimentof the proposed disclosure where an over-current protection circuit isimplemented composed of a current sensing resistor 48 and an activelyswitched low voltage enhancement mode transistor 49. Many of thefeatures of this embodiment are similar to those of FIG. 6 and thereforecarry the same reference numerals, i.e., the semiconductor substrate 4,substrate terminal 5, transition layer 3, GaN layer 2, AlGaN layer 1,active pGaN layer 11, active gate terminal 10, surface passivationdielectric 7, low voltage source terminal 8, high voltage drain terminal9, SiO₂ passivation layer 6, isolation region 13, auxiliary AlGaN layer17, auxiliary pGaN layer 14, auxiliary gate 15, first additionalterminal 16, second additional terminal 12 and second auxiliarytransistor 34. In this embodiment, the active area of the active (highvoltage) transistor is divided into two regions forming two transistorsin parallel. The drain and gate terminals of the two transistors areelectrically connected. The two transistors in parallel are a lowresistance (main power) transistor 55 and a high resistance (currentsensing) transistor 54 comparatively. The first terminal of the currentsensing resistor 48 is connected to the source terminal of the highresistance transistor 54. The potential at the gate terminal of theenhancement mode transistor 49 is increased as the current through thecurrent sensing resistor 48 is increased. When the current throughresistive element 48 reaches a critical value the enhancement modetransistor 49 turns on providing a reduction in the resistance of thepath between the gate 10 and source 8 of the active (high voltage)device thus limiting the potential on the active gate terminal 10. Thecircuit described can protect the circuit from an over-current event.

FIG. 14 shows a circuit schematic representation of a further embodimentof the proposed disclosure where an over-current protection circuit isimplemented composed of a current sensing resistor 48 and an activelyswitched low voltage depletion mode transistor 47. Many of the featuresof this embodiment are similar to those of FIG. 6 and therefore carrythe same reference numerals, i.e., the semiconductor substrate 4,substrate terminal 5, transition layer 3, GaN layer 2, AlGaN layer 1,active pGaN layer 11, active gate terminal 10, surface passivationdielectric 7, low voltage source terminal 8, high voltage drain terminal9, SiO₂ passivation layer 6, isolation region 13, auxiliary AlGaN layer17, auxiliary pGaN layer 14, auxiliary gate 15, first additionalterminal 16, second additional terminal 12 and second auxiliarytransistor 34. In this embodiment, the active area of the active (highvoltage) transistor is divided into two isolated regions forming twotransistors in parallel. The drain and gate terminals of the twotransistors are electrically connected. The two transistors in parallelare a low resistance (main power) transistor 55 and a high resistance(current sensing) transistor 54 comparatively. The first terminal of thecurrent sensing resistor 48 is connected to the source terminal of thehigh resistance transistor 54. The potential at the gate terminal of thedepletion mode transistor 47 is increased as the current through theresistive element 48 is increased. As the current through resistiveelement 48 increases the resistance of the depletion mode transistor 49can decrease providing a reduction in the resistance of the path betweenthe gate 10 and source 8 of the active (high voltage) device thuslimiting the potential on the active gate terminal 10. The circuitdescribed can protect the circuit from an over-current event.

FIG. 15 shows a circuit schematic representation of a further embodimentof the proposed disclosure where an active Miller clamp circuit isimplemented composed of a resistor 52, an actively switched low voltageenhancement mode transistor 50 and an actively switched depletion modetransistor 51. Many of the features of this embodiment are similar tothose of FIG. 6 and therefore carry the same reference numerals, i.e.,the semiconductor substrate 4, substrate terminal 5, transition layer 3,GaN layer 2, AlGaN layer 1, active pGaN layer 11, active gate terminal10, surface passivation dielectric 7, low voltage source terminal 8,high voltage drain terminal 9, SiO₂ passivation layer 6, isolationregion 13, auxiliary AlGaN layer 17, auxiliary pGaN layer 14, auxiliarygate 15, first additional terminal 16, second additional terminal 12 andsecond auxiliary transistor 34. In this embodiment, the active Millerclamp circuit is implemented to offer an additional pull-down networkfor the active device gate terminal 10 during the device turn-offtransient.

FIG. 16 shows a circuit schematic representation of a further embodimentof the proposed disclosure where an active Miller clamp circuit isimplemented composed of a resistor 52, an actively switched low voltageenhancement mode transistor 50 and an actively switched enhancement modetransistor 53. Many of the features of this embodiment are similar tothose of FIG. 6 and therefore carry the same reference numerals, i.e.,the semiconductor substrate 4, substrate terminal 5, transition layer 3,GaN layer 2, AlGaN layer 1, active pGaN layer 11, active gate terminal10, surface passivation dielectric 7, low voltage source terminal 8,high voltage drain terminal 9, SiO₂ passivation layer 6, isolationregion 13, auxiliary AlGaN layer 17, auxiliary pGaN layer 14, auxiliarygate 15, first additional terminal 16, second additional terminal 12 andsecond auxiliary transistor 34. In this embodiment, the active Millerclamp circuit is implemented to offer an additional pull-down networkfor the active device gate terminal 10 during the device turn-offtransient.

FIG. 17 illustrates a schematic representation of a cross section of theactive area of a proposed depletion mode device in prior art which canbe used as the actively switched transistor in locations 46, 47, 51, 58,59, 60.

FIG. 18 illustrates a three dimensional schematic representation of theactive area of a proposed depletion mode device with pGaN islands (notfound in prior art) which can be used as the actively switchedtransistor in locations 46, 47, 51, 58, 59, 60.

FIG. 19 illustrates a three dimensional schematic representation of theactive area of the depletion mode device with pGaN islands shown in FIG.18 operated in diode mode and can be used in locations 34 58 59.

FIGS. 59 and 60 show schematic representations of two furtherembodiments of a transistor with p-GaN islands 11. In FIG. 59, they arearranged in such a way that an

S-shaped meander is formed between the islands 11. The p-GaN islands areoperatively connected through a contact layer 10 to the common gateterminal 59. FIG. 60 is a similar embodiment with three rows of p-GaNislands 11 arranged to form a labyrinth shaped 2DEG between the islands.

FIG. 71 shows an example of a current-voltage characteristic of theD-HEMT transistor illustrated in FIGS. 59 and 60.

The D-HEMT with p-GaN islands illustrated in FIGS. 59 and 60, when inthe high resistance mode (gate bias with respect to source bias isbetween the first and second threshold voltage level), may feature asaturation current behaviour limiting the current at strong forwardbias. The extent to which the current saturates may be affected by thedistance between the pGaN islands where the smaller the distance betweenthe pGaN islands, the stronger the current saturation observed. Anexample of this saturation is illustrated in FIG. 71.

FIG. 20 shows the transfer characteristic of the proposed depletion modedevice shown in FIG. 18.

FIG. 21 illustrates the cross-section of an additional embodimentaccording to a second aspect of the proposed invention. The featuresshown in FIG. 21 carry the same reference numerals as those shown inFIG. 2. In this embodiment, the first additional terminal 16 and theauxiliary gate terminal 15 are not operatively connected.

FIG. 22 shows a schematic illustration of the structure of FIG. 21, andcorresponding features of this figure use the same reference numerals.In this embodiment, a range of components may be added between theauxiliary gate terminal 15 and the first additional terminal 16. Merelyfor example, these components may include, but are not limited to, anyone or more of resistive elements, passive elements and current sources.Further illustrative examples of such embodiments are presented herein.

In FIG. 23 a Gallium Nitride (GaN) chip 1000 (also referred to as asmart GaN power device or a GaN power or high voltage integratedcircuit) is shown according to an embodiment of the second aspect ofthis invention. The GaN chip may comprise at least three terminals.These at least three terminals may include one or more of a high voltageterminal, a low voltage terminal and a control terminal. The chip 1000may further comprise one or more main power heterojunction transistors500 with an internal gate. The source and drain terminals of transistor500 may be connected to the low voltage and high voltage terminals ofthe GaN chip respectively. Chip 1000 may further comprise a currentcontrol circuit 530, a pull-down circuit 520 and/or an auxiliary gatecircuit 510. The auxiliary gate circuit 510 may contain at least onelow-voltage heterojunction transistor (also referred to as an auxiliarytransistor) with an internal gate.

The auxiliary gate circuit 510 may be operatively connected to at leastthe internal gate of the one main power heterojunction transistor 500 bya first connection, and may further comprise a second connection tooperatively connect the auxiliary gate 510 to the control terminal. Athird connection of the auxiliary gate circuit 510 may operativelyconnect the internal gate of the low-voltage heterojunction transistorof auxiliary gate circuit 510 to the pull down circuit 520.

In addition to the at least one connection to the auxiliary gatecircuit, pull-down circuit 520 may comprise at least one connection tothe current control circuit and at least one connection to the sourceterminal of the main power heterojunction transistor 500.

Current control circuit 530 may comprise at least one connection to eachof the control terminal, auxiliary gate circuit 510 and pull downcircuit 520.

The auxiliary gate 510 may partly control the voltage and the currentlevels into the internal gate of the main power heterojunctiontransistor 500. The current control circuit 530 may control the currentlevel into pull down circuit 520 and in conjunction with the pull downcircuit may further determine the voltage level applied to the internalgate of the low-voltage heterojunction transistor of auxiliary gate 510.The pull-down circuit in turn may actively pull down the gate voltage ofthe low-voltage heterojunction transistor in order to clamp the voltageof the internal gate of the main power heterojunction transistor.

With reference to FIGS. 22 and 23, in some embodiments the auxiliarygate terminal 15 of auxiliary gate block 510 may be connected through orvia current control block 530 to the first additional terminal 16 ofauxiliary gate block 510. Auxiliary gate terminal 15 may be furtherconnected through or via the pull-down circuit block 520 to the sourceterminal 8 of active device block 500.

The portion of the auxiliary 2DEG under the auxiliary pGaN gate 14 maybe depleted when the auxiliary gate terminal 15 is at or close to 0V. Asthe first additional terminal bias is increased, the potential on bothterminals 15, 16 may increase and the 2DEG may begin forming under pGaNgate 14. The 2DEG formed under pGaN gate 14 may connect to the (alreadyformed) 2DEG layers under the first and second additional terminals 16,12. By connecting these 2DEG layers, a 2DEG connection may be formedbetween the first and second additional terminals 12, 16.

As the second additional terminal 12 is connected to the active gate 10the device can now turn on. A positive shift in the device thresholdvoltage is observed using this structure as not all of the potentialapplied to the first additional terminal 16 is transferred to the activegate (internal gate) 10. Part of this potential is dropped across theauxiliary gate 510 and only part is transferred to the second additionalterminal 12 which is connected to the active gate (internal gate) 10.Advantageously, this enables an increase in the threshold voltagewithout compromising the on-state resistance of the device, as discussedbelow.

FIG. 24 shows an example of the relationship between the external gatevoltage bias (GaN chip control terminal bias) 2501 and the active gatevoltage (internal gate voltage) 2502 according to one embodiment of theinvention. When the external gate voltage signal rises initially (up toauxiliary gate transistor Vth) the auxiliary gate transistor has a highresistance. The majority of the potential applied is dropped across theauxiliary gate transistor and the potential of the active gate terminalremains close to 0V. When the external gate voltage signal reaches theauxiliary gate transistor Vth the auxiliary transistor becomes lessresistive and the potential of the active gate terminal starts rising.

A threshold voltage increase is therefore achieved in the GaN chipmulti-block HEMT without any compromise in the on-state resistance ofthe device. A positive shift (as shown in graph 2500) in the devicethreshold voltage is observed using this structure as not all of thepotential applied to the external gate is transferred to the active gate(part of this potential is used to form the auxiliary 2DEG under theauxiliary gate) and only part is transferred to the terminal 12 which isconnected to the active gate 10.

When the external gate 16 bias voltage reaches a pre-designed level,pull-down circuit block 520 becomes operational and pulls the gate 15 ofthe auxiliary transistor towards the active transistor source terminal 8potential. The auxiliary transistor has a high resistance in thiscondition, therefore any additional external gate potential is droppedacross the auxiliary transistor and the active gate terminal potentialremains approximately constant with the external gate voltage signalrising, for example to at least approximately 20V.

The design of the current control block 530 and pull-down circuit block520 determines the potential where the active gate terminal is clamped.

Several illustrative examples are included herein with differentimplementations of the functional blocks 510, 520, 530. Note that thelist of examples presented is not exhaustive and any combination of thedifferent implementations for each block can be considered under thescope of this invention. This includes the several examples of theauxiliary gate presented above. Furthermore, any or all of theprotection and control circuits (over-voltage, overcurrent, millerclamp) presented above may also be combined with the functional blockspresented in FIG. 23.

FIG. 25 shows a schematic representation of one embodiment the GaN chip1000 a of the proposed invention. Auxiliary gate block 510 a comprisesan enhancement mode low voltage HEMT, current control block 530 acomprises a resistor and the pull-down circuit 520 a comprises a HEMT inthreshold multiplier configuration. The threshold multiplierconfiguration in this embodiment comprises a potential divider and apull-down enhancement mode HEMT where the midpoint of the potentialdivider is connected to the gate terminal of the pull-down HEMT. In thisembodiment, the top of the potential divider is connected to the drainof the pull-down enhancement mode HEMT and the gate terminal of theauxiliary gate block HEMT.

FIG. 26 shows a schematic representation of a further embodiment of theGaN chip 1000 b of the proposed invention where the auxiliary gate block510 b comprises an enhancement mode low voltage HEMT. The currentcontrol block 530 b comprises a resistor in parallel with an RC circuit.The RC circuit in parallel can improve the device dynamic characteristicduring turn-on and turn-off transients. The pull-down circuit 520 bcomprises a HEMT in threshold multiplier configuration with a passiveelement in parallel. The passive element can improve the device dynamiccharacteristic during turn-on and turn-off transients.

FIG. 27 shows a schematic representation of a further embodiment of theGaN chip 1000 c of the proposed invention. The auxiliary gate block 510c comprises an enhancement mode low voltage HEMT and a Schottky or p-ndiode in parallel. In this embodiment, a low on-state voltage diode isconnected in parallel between the drain 16 and the source 12 of theauxiliary transistor. The parallel diode acts as pull-down networkduring the turn-off of the overall configuration connecting to groundthe gate terminal 10 of the active GaN transistor. When a positive bias(known as on-state) is applied to the external gate terminal 16, thediode will be reverse-biased and zero current will flow through it,leaving unaffected the electrical behaviour of the overall high-voltageconfiguration. When a zero bias (off-state) is applied to the auxiliarygate 15 the diode is forward biased and the turn-off current flowingthrough it will discharge the gate capacitance of the active transistor,thus enabling the switching off of the overall configuration. Inoff-state, the gate of the active device 10 will remain biased to aminimum voltage equal to the turn-on voltage of the diode. The diodewill therefore be designed in such a way that its turn-on voltage willbe as low as possible, ideally few mV. The current control block 530 ccomprises a current source using a low voltage depletion mode HEMT and aresistor. The resistor value can be adjusted to set the maximum currentlevel that can flow through the current source. The pull-down circuit520 c comprises a HEMT in threshold multiplier configuration.

FIG. 28 shows a schematic representation of a further embodiment of theGaN chip 1000 d of the proposed invention where the auxiliary gate block510 d comprises an enhancement mode low voltage HEMT. The currentcontrol block 530 d comprises a current source using a low voltagedepletion mode HEMT and a resistor. The pull-down circuit 520 dcomprises a HEMT in threshold multiplier configuration.

FIG. 29 shows a schematic representation of a further embodiment the GaNchip 1000 e of the proposed invention where the auxiliary gate block 510e comprises an enhancement mode low voltage HEMT. Furthermore, in thisembodiment, a second auxiliary transistor (could be advantageouslylow-voltage) is connected in parallel with the first auxiliarytransistor in the auxiliary gate block where the drain terminal 16 ofthe first auxiliary transistor is connected to the drain terminal of thesecond auxiliary transistor and the source terminal 12 of the firstauxiliary transistor is connected to the source (gate) terminal of thesecond auxiliary transistor. In this embodiment, the pull-down networkduring the turn-off of the overall configuration is a second auxiliarytransistor. This is similar to the embodiment shown in FIG. 27 bututilises a second auxiliary transistor rather than a diode. The currentcontrol block 530 e comprises a current source using a low voltagedepletion mode HEMT and resistor. The pull-down circuit 520 e comprisesa HEMT in threshold multiplier configuration.

FIG. 30 shows a schematic representation of a further embodiment the GaNchip 1000 f of the proposed invention where the auxiliary gate block 510f comprises an enhancement mode low voltage HEMT. Furthermore, in thisembodiment, a second auxiliary transistor is connected in parallel withthe first auxiliary transistor as outlined in the embodiment in FIG. 29.The current control block 530 f comprises a current source using a lowvoltage depletion mode HEMT and resistor. The pull-down circuit 520 fcomprises a HEMT in threshold multiplier configuration. In thisembodiment, the threshold multiplier further comprises a current sourcein parallel with one of the resistors in the potential divider of thethreshold multiplier circuit. The inclusion of the current sourceprovides stability in temperature in the value of the clamped voltageachieved on the active gate of the high voltage transistor 500 when thevoltage signal on the external gate terminal is high.

FIG. 31 shows a schematic representation of a further embodiment the GaNchip 1000 j of the proposed invention where the auxiliary gate block 510j comprises an enhancement mode low voltage HEMT. The current controlblock 530 j comprises a current source using a low voltage depletionmode HEMT and resistor. The pull-down circuit 520 j comprises a HEMT inthreshold multiplier configuration similar to previous embodiments whichcomprise a potential divider and an enhancement mode pull-down HEMT.

However, in this embodiment, the resistor at the top of the potentialdivider, which in previous embodiments was connected to the drainterminal of the enhancement mode pull-down HEMT, is alternativelyconnected to the source terminal of the depletion mode HEMT used in thecurrent source of the control block.

FIGS. 46 and 47 show further embodiments of the invention with thepull-down circuit comprising a second input. This second input may be asupply or regulated voltage stemming from an external terminal orgenerated on the chip. The second input may be used as a referencevoltage.

FIG. 48 shows a schematic representation of a further embodiment of thepull-down circuit 520 k. The pull-down circuit block comprises a voltagesource and a capacitor in series with a HEMT in a diode configuration.In this embodiment, the resulting voltage drop across the pull-downcircuit is the sum of the voltage level of the voltage source and thevoltage drop across the HEMT at the current level defined by the currentcontrol block. When zero volts, or a small voltage (for example below1V) or a negative voltage is applied to the external gate terminal 16(off-state), the HEMT in diode configuration will be reversed biased.FIG. 49 shows a similar embodiment of the pull-down circuit where theHEMT is not in diode configuration but rather in a threshold multiplierconfiguration using two resistive elements. Other examples include theuse of non-linear elements in the threshold multiplier configuration.

FIG. 32 shows a block diagram schematic representation of a furtherembodiment of the proposed invention. In this embodiment, someadditional functional blocks are included compared to the embodimentshown in FIG. 23. In this embodiment, the auxiliary gate block, currentcontrol block and pull-down circuit block are included as in previousembodiments. An integrated active Miller clamp is also included.

FIG. 61 shows the schematics of an embodiment of a logic inverter 560 acomprising a resistive element as a pull-up circuit and an enhancementmode transistor on the low side, similar to those shown in FIGS. 15 and16 driving the Miller clamp transistor.

FIG. 62 shows a further embodiment of the logic inverter 560 bcomprising a current source circuit rather than a resistive element inseries with an enhancement mode transistor in which the current sourceconsists of a depletion mode transistor and a resistive element.

In FIG. 63, an embodiment of the logic inverter 560 c is shown thatconsists of two stages. In a multi-stage inverter, all stages comprisean enhancement transistor on the low side with the gate connected to theinput signal. Both stages comprise a pull-up circuit, the one of thesecond stage is controlled by the output of the first stage. In thisembodiment of a two-stage inverter, the pull-up circuit of the firststage comprises a current source as described above. The pull-up circuitof the second stage comprises a resistive element and a depletion-modetransistor in series where the gate of the depletion-mode transistor isconnected to the output of the first stage. In this embodiment thecapacitance of the output of the first stage may be very small, leadingto a fast switching time even at a small current consumption. Therefore,the gate of the depletion-mode transistor of the second stage will risefaster than in a current source arrangement. Therefore, this arrangementmay lead to a faster switching time at a given load and a given currentconsumption.

A further embodiment of a two-stage inverter 560 d is shown in FIG. 64.An additional enhancement transistor is connected to the pull-up circuitof the second stage. This transistor has the gate connected to theoutput of a previous stage and is connected in parallel to the resistiveelement of the pull-up circuit. During switching to high, the output ofthe first stage is at a higher voltage compared to the output of thesecond stage. Therefore, the gate of the additional pull-up circuittransistor being positively biased compared to its source terminalreduces its resistance and increases the current into the output signal.Before and after switching, the output of the first stage and secondstage are the same, and the gate of the additional pull-up circuittransistor has zero bias compared to its source bias. The increasedcurrent during switching leads to a faster switching time for a givenload, such as the actively switched transistor of a Miller clamp,without compromising current consumption in the high or low state.

In FIG. 65, a further embodiment of a two-stage inverter 560 e is shown.Compared to FIG. 63, the additional pull-up circuit enhancementtransistor is connected between the dc voltage rail and the output andworks similarly as described in FIG. 64.

The active Miller clamp circuit (for example in FIG. 32) is implementedto offer an additional pull-down network for the active device gateterminal 10 during the device turn-off transient. The active Millerclamp circuit may comprise a monolithically integrated Miller clamptransistor 570, a logic inverter 560, an external gate signal to logicsignal conversion 540 and/or a DC to DC block 550 to produce anappropriate inverter VDD rail.

The transistor 570 may include a low voltage enhancement mode HEMT asillustrated in this embodiment. The logic inverter 560 may include a lowvoltage enhancement mode

HEMT and a resistor (similar to the inverter circuit illustrated in FIG.16). However, this is merely provided as an example configuration, andother logic inverter designs (as illustrated in FIGS. 61, 62, 63, 64 and65) could be utilised in place of or in addition to this. Theenhancement mode device used in the inverter may be formed in the sameprocess step as the active high voltage transistor. Therefore, the upperlimit of the voltage signal that can be applied to the gate of theinverter transistor might be lower than the external gate signal. The Vgto logic block 540 may be used to reduce the external gate voltagesignal to a voltage signal appropriate for use with a p-GaN technologyenhancement mode HEMT.

The integrated Miller clamp transistor may receive a signal close to VDDto its gate terminal when the output of the inverter is high. Therefore,if the VDD rail available is higher than the peak gate voltage that theintegrated clamp resistor can tolerate then a DC/DC step 550 may beintegrated into the GaN chip multi-block power device to reduce the VDDrail to a desirable level.

FIG. 50 shows the block diagram of a voltage regulator (or DC/DC block)550 connected to the input of the receiving circuit (for example thelogic inverter) through a decoupling circuit 580. An embodiment with adecoupling circuit may protect the inverter from current spikes orvoltage excursions induced from the voltage source. These current spikesor voltage excursions may be a result of electromagnetic coupling of thecircuit to other elements of the chip or the system, in particular, fastvoltage and current slopes and may originate from the input to the DC/DCblock, or within the DC/DC block. Overvoltage of the DC voltage maydestroy the inverter, undervoltage may lead to malfunction.

In FIG. 51, an exemplary embodiment of the decoupling circuit is shownwhere the decoupling circuit 580 a consists of a series resistiveelement and a capacitor across the input voltage of the inverter. Inanother embodiment, shown in FIG. 52, the resistive element may bereplaced with a current source formed of a depletion HEMT and aresistive element. FIGS. 53 and 54 show exemplary embodiments, where atransistor is added to the current source in parallel to the currentsource or in parallel to the resistive element to adjust the currentlimit through the current source. When the additional transistor is in alow resistive state the coupling is strong for high current supply. Whenthe additional transistor is in a high resistive state, the coupling isweak (good decoupling) but only a low current can be supplied throughthe decoupling circuit. The additional HEMT allows adjusting couplingand current limit to varying operating status.

FIG. 55 shows the decoupling circuit 580 e comprising a current sourceas in FIG. 52 and an additional HEMT in parallel to the capacitiveelement. This additional HEMT allows sinking the current in case of acurrent spike and may be effective against overvoltage. In thisexemplary embodiment, the additional HEMT is turned on by a resistiveand capacitive voltage divider on the input side of the decouplingcircuit. When the input voltage rises to a certain level or exceeds acertain rate the gate of the additional HEMT is increased to turn theHEMT on and to sink excess current.

FIG. 56 shows an additional embodiment of a decoupling circuit 580 c(similar to the decoupling circuit 580 e shown in FIG. 55) in which theadditional HEMT in parallel with the current source is controlled byhaving its gate connected to the gate voltage of the active HEMT 500. Inthis embodiment, the coupling is strong when the active HEMT is in theon-state, weak when the active HEMT is off.

The described decoupling circuits may be applied not just for the inputof the inverter but for any dc signal or dc supply voltage on the chip.

FIG. 33 shows a schematic representation of a further embodiment the GaNchip 3000 a of the proposed invention where the auxiliary gate block 610a comprises a depletion mode low voltage HEMT. The current control block630 a comprises a resistive element. The pull-down circuit 620 acomprises a HEMT in threshold multiplier configuration. The operation ofthe GaN chip multi-block power device illustrated in this embodiment issimilar to the operation of the device illustrated in FIG. 25 inachieving a clamped voltage signal on the active gate terminal (internalgate terminal) of the high voltage HEMT (the main power heterojunctiontransistor) 500 when the external voltage signal exceeds apre-determined (by design) level. The use of a depletion mode transistorin the auxiliary gate block in this embodiment might not be as effectivein providing an increased threshold voltage for the GaN chip powerdevice 3000 a, compared to the GaN chip power device 1000 a. The lowvoltage depletion mode HEMT may be more effective in providing aturn-off path as part of the turn-off network of the device as thechannel in the depletion-mode transistor is present when the potentialon the active gate is high and the potential at the external gateterminal is low.

FIG. 34 shows a schematic representation of a further embodiment of theGaN chip 3000 b of the proposed invention where the auxiliary gate block610 b comprises a depletion mode low voltage HEMT. In this embodiment, asecond auxiliary transistor (which may advantageously be a low-voltagetransistor) is connected in parallel with the first auxiliary transistorin the auxiliary gate block where the drain terminal 16 of the firstauxiliary transistor is connected to the drain terminal of the secondauxiliary transistor and the source terminal 12 of the first auxiliarytransistor is connected to the source (gate) terminal of the secondauxiliary transistor. In this embodiment, the second auxiliarytransistor is included as an additional pull-down network during theturn-off of the high voltage transistor 500. The current control block630 e comprises a current source using a low voltage depletion mode HEMTand resistor. The pull-down circuit 620 e comprises a HEMT in thresholdmultiplier configuration.

FIG. 35 shows a schematic representation of a further embodiment the GaNchip 3000 d of the proposed invention where the auxiliary gate block 610d comprises a depletion mode low voltage HEMT. Furthermore, in thisembodiment, a second depletion mode auxiliary transistor (could beadvantageously low-voltage) is connected in parallel with the firstauxiliary transistor in the auxiliary gate block where the drainterminal 16 of the first auxiliary transistor is connected to the drainterminal of the second auxiliary transistor and the source terminal 12of the first auxiliary transistor is connected to the source terminal ofthe second auxiliary transistor. The gate terminal of the secondauxiliary transistor is connected to the source terminal of the highvoltage transistor 500. In this embodiment, the second depletion modeauxiliary transistor is included as an additional current path duringthe turn-on of the high voltage transistor 500. When the external gatesignal goes high the second depletion-mode transistor is in saturationmode and provides an additional conduction path for charging thegate-source capacitance of the high voltage transistor 500. As thevoltage of the active gate terminal rises above the threshold voltage ofthe second depletion mode transistor that conduction path becomes veryresistive. The current control block 630 e comprises a current sourceusing a low voltage depletion mode HEMT and resistor. The pull-downcircuit 620 e comprises a HEMT in threshold multiplier configuration.

FIG. 36 shows a schematic representation of a further embodiment the GaNchip 5000 b of the proposed invention where the auxiliary gate block 810b comprises an enhancement mode low voltage HEMT. The current controlblock 830 b comprises a current source using a low voltage depletionmode HEMT and resistor. The pull-down circuit 820 b comprises a HEMT inthreshold multiplier configuration which comprises a potential dividerand a pull-down enhancement mode HEMT where the midpoint of thepotential divider is connected to the gate terminal of the pull-downHEMT. In this embodiment, the top of the potential divider is connectedto the active gate terminal rather than the drain of the pull-downenhancement mode HEMT as in previous embodiments.

In FIG. 37 the top of the potential divider is connected to the activegate terminal, the potential divider comprises a number of source-gateconnected E-HEMTs in series 821 c with the resistors shown in previousembodiments. While FIG. 37 shows two HEMT in series, a different numbermay be used. These HEMTs are one possible method to adjust the voltagelevel that is required to be reached on the active gate terminal beforethe pull-down enhancement mode HEMT becomes operational.

FIG. 38 shows another method for adjusting the voltage level required tobe reached on the active gate terminal before the pull-down enhancementmode HEMT becomes operational. FIG. 38 utilises an additional HEMT inthreshold multiplier configuration 821 d.

FIG. 39 shows a schematic representation of a further embodiment the GaNchip 6000 a of the proposed invention where the auxiliary gate block 910a comprises an enhancement mode low voltage HEMT. The current controlblock 930 a comprises a current source using a low voltage depletionmode HEMT and resistor. The pull-down circuit 920 a comprises a HEMT inthreshold multiplier configuration which comprises a potential dividerwhere the midpoint of the potential divider is connected to the gateterminal of the pull-down HEMT similar to previous embodiments. However,in this embodiment, the potential divider is connected to the externalgate terminal rather than the gate terminal of the auxiliary transistor.In addition, a further HEMT in threshold multiplier configuration may beincluded between the gate and source terminal of the enhancement modepull-down HEMT. This additional threshold multiplier acts to limitvoltage on the gate terminal of the pull-down transistor. Thisadditional threshold multiplier may alternatively be implemented usingone or more diodes in series.

FIG. 40 shows a schematic representation of a further embodiment the GaNchip 6000 b of the proposed invention where the auxiliary gate block 910b comprises an enhancement mode low voltage HEMT. The current controlblock 930 b comprises a current source using a low voltage depletionmode HEMT and resistor. The pull-down circuit 920 b comprises apull-down enhancement mode HEMT with the gate connected to the output ofa voltage divider similar to other embodiments. In this embodiment, thevoltage divider is connected to the external gate terminal and consistsof a current source and a HEMT in threshold multiplier configuration.The current source is implemented using a low voltage depletion modeHEMT and a resistor. The output of the voltage (potential) divider isthe gate of the additional low-voltage HEMT.

In further embodiments, the gate of the pull-down HEMT may be controlledby an additional external signal, preferably through a VG to Vlogicregulator as described above, or by the output of an additional circuitintegrated on the GaN device providing functions such as over-currentprotection, under-voltage lock-out, supply-voltage over-voltageprotection, logic inverter or others.

In further embodiments, the exemplary GaN chip circuit 7000 illustratedin FIG. 69 may comprise one or several enable or disable functions topermanently or temporarily enable or disable the active HEMT,independent of the control signal applied. In FIG. 69, several exemplaryembodiments are shown of enable or disable functions. With HEMT 595 a,the disable function is realised as a HEMT across the pull-down circuit520 limiting the voltage of the gate of the auxiliary gate.

HEMT 595 b is integrated with the inverter driving the Miller clamptransistor 570. The inverter and HEMT 595 b are forming a logic NANDfunction.

A third exemplary embodiment is shown in FIG. 69 where HEMT 595 c is inseries with the Miller clamp in a logic NAND connection, meaning thatboth the Miller clamp transistor and the disable transistor must be offto enable the gate voltage of the active GaN HEMT 500 to rise.

In a fourth exemplary embodiment, HEMT 595 d is connected in parallel tothe Miller clamp in a logic NOR connection, meaning that either theMiller clamp or the disable HEMT 595 d may reduce the gate voltage ofthe active GaN HEMT 500.

A further embodiment of the invention is shown in FIG. 66 comprising acurrent control circuit 530 that is connected to a separate input(VINPUT2) than the auxiliary gate transistor. Further, in the samefigure, the integration of a disable function 595 e is shown in parallelto the pull-down circuit 520. While the disable function is active, thegate of the active GaN HEMT 500 is not affected by the input signal onthe first additional terminal (VINPUT1). In this exemplary embodiment,the disable block 595 e consists of an enhancement HEMT and a logicinverter allowing the application of a high signal to enable the turn-onof the device. The disable function 595 e does not actively reduce (turnoff) the gate of the active GaN HEMT 500. To do this, a Miller clamptransistor 570 as shown in FIG. 32 may be integrated. With the Millerclamp arrangement and disable function shown here, a gate driverfunctionality is realised in which the voltage on the first additionalterminal (VINPUT1) may be kept constant and the disable and Miller clampmay control the gate of the active GaN HEMT 500.

A further embodiment of the invention is shown in FIG. 67 in which thecurrent control block 530 m is actively switched. In this embodiment,the control signal to the current control block stems from the enableand disable input. Compared to the arrangement in FIG. 66, the currentis reduced when the disable function is active, reducing the currentconsumption when the device is disabled.

Another exemplary embodiment is presented in FIG. 68. The pull-downcircuit 520 k consists of a voltage source VDD3 and an enhancement HEMTwith drain connected to the gate, as described earlier in thisinvention. An enable/disable circuit 595 f is in parallel to thepull-down circuit as in FIG. 67. The current control block 530 n in thisembodiment contains an additional voltage drop where a voltage VDD2 isgenerated from the voltage at the first additional terminal (VINPUT1).The voltage drop between VI NPUT1 and VDD2 is achieved through a voltageregulator 530 na based on an embodiment of the gate interface circuitdescribed in this invention. The current control block is activelycontrolled with a signal from the enable or disable terminal. The activecontrol may be realised using a logic inverter driving the gate of adepletion HEMT 531 forming the current source. A logic inverter withmore than one stage, as described earlier in this invention, may be usedto drive the depletion HEMT 531. Additionally, an enhancement HEMT 532is connected in parallel to the current source with the gate of theenhancement HEMT connected to an internal node of the current controlblock. This additional enhancement HEMT may provide an additionalcurrent path during the switching event when the disable function isreleased.

FIG. 41 illustrates an interdigitated device layout of a furtherembodiment of the disclosure incorporating an auxiliary gate structure.Many features of this embodiment are similar to those shown in FIG. 21and therefore carry the same reference numerals, i.e., active gateterminal 10, low voltage source terminal 8, high voltage drain terminal9, first additional terminal 16 and second additional terminal 12. Alsoshown in this illustration are the source pad metal 18, drain pad metal19, and gate pad metal 20. However, in this embodiment, rather than thegate pad metal 20 being contacted to the gate fingers 10 directly as ina prior art device, it is connected to the auxiliary gate terminal 16.The gate fingers in the interdigitated structure are directly connectedto the second additional terminal 12. Note that in this layout, as inthe cross-sections in previous embodiments, an isolation layer existsbetween the 2DEG in the auxiliary gate and the active device. Theadditional operational blocks in this device are also illustrated:auxiliary gate block 510, pull-down circuit block 520, current controlblock 530. The connections of the different blocks can be made usinginterconnection metal layers 210.

FIG. 42 illustrates an interdigitated device layout of a furtherembodiment of the disclosure in which the auxiliary gate and terminalregions are placed below the source pad metal. Similarly these circuitscould be placed under the gate pad or the drain pad (not shown). Manyfeatures of this embodiment are similar to those shown in FIG. 41 andtherefore carry the same reference numerals, i.e., active gate terminal10, low voltage source terminal 8, high voltage drain terminal 9, firstadditional terminal 16, second additional terminal 12, source pad metal18, drain pad metal 19, gate pad metal 20, auxiliary gate block 510,pull-down circuit block 520, current control block 530, interconnectionmetal 210. However, in this embodiment, the auxiliary gate block,current control block and pull-down circuit block are placed below thesource pad metal 18. Intermetal vias 220 can connect blocks at differentmetal layers in the process. Less additional wafer area would be neededto include the additional blocks compared to a prior art design. Notethat in this illustration the additional blocks are placed under thesource pad metal however this disclosure is intended to include designswhere the additional blocks may be placed under other pads present inthe integrated circuit layout.

FIG. 43 shows a block diagram of a further embodiment of the proposeddisclosure where any of the embodiments of the GaN chip power device 35are placed in a half-bridge configuration, where the external gates ofthe two power devices (both high and low side) are connected to gatedriving blocks which are in turn connected to logic blocks. Thedifferent components and blocks included in the figure can be discretecomponents or connected monolithically. This demonstrates differentexamples of possible monolithic integration 36, 37, 38 while utilisingthe concept of the auxiliary gate.

FIG. 44 shows a circuit schematic representation of a further embodimentof the proposed disclosure where the GaN chip power device 35 accordingto this disclosure is connected in a standard three-phase half-bridgeconfiguration.

FIG. 57 shows a schematic representation of an embodiment of the currentcontrol block 530 k with a current reduction feature. To a conventionalcurrent source consisting of a depletion HEMT and resistive element, anadditional enhancement mode HEMT is added, in parallel to the resistiveelement. Note that during off-state of the active GaN HEMT 500, theoutput of the current control block is at a low voltage, and in theon-state it is at a higher voltage. The gate of the additionalenhancement mode HEMT is at a fixed voltage. Therefore, the resistanceof the additional enhancement mode HEMT is higher in on-state than inoff-state. This leads to the desired reduction of the current in thecurrent control block during on-state of the active GaN HEMT 500. Inaddition, the gate of the additional HEMT can be actively controlled tofurther modulate the current level through the current control block.Further, the additional enhancement HEMT may be connected in parallel tothe entire current source rather than only the resistive element.

FIG. 58 shows a similar embodiment of a current control block with acurrent reduction feature but using an additional depletion HEMT insteadof an additional enhancement HEMT.

FIG. 45 shows a schematic representation of an embodiment of a shieldingand/or decoupling structure. The purpose of shielding and/or decouplingstructure is to reduce or eliminate the influence of one part of thechip, e.g. the active GaN device (main power HEMT), on a different partof the chip, e.g. the pull-down circuit, via electro-magnetic coupling.The shielding and/or decoupling structures can be below, above, on thesides or in the vicinity of either or both of the two parts of the chip.FIG. 45 shows an example shielding and/or decoupling structure 61, 62situated laterally between two parts, or structures, 60, 66 of the chip.In this example, the decoupling structure comprises a plurality of 2DEGstructures 61, 62. These 2DEG structures 61, 62 are connected to acontrolled potential, e.g. to the first terminal of the active GaNdevice, through an ohmic contact layer 64 and operatively connectedthrough vias 65 to other metal layers. Areas 60 and 66 may comprisearrangements of HEMTs, capacitive and resistive elements and electricalconnections. Areas 60 and 66 may further be fully or partially shieldedby layers above or below.

FIG. 70 shows a block diagram of a further embodiment of the disclosurewith several GaN chip power devices. In this embodiment, the powerdevices 500 a, 500 b and the gate interfaces 8000 a, 8000 b share thelow-voltage terminal (source). FIG. 70 shows how some of the externalcontrol or supply signals are connected to only one gate interface.Other control or supply signals are connected between several gateinterfaces. This is the result of the blocks auxiliary gate circuit,pull-down circuit and current control-circuit or parts thereof beingshared among the several main power devices for more compact solutions.For example, a voltage regulated on one gate interface block may be useddirectly in another gate interface block. This avoids duplication ofsub-circuits and saves chip area.

It will be appreciated that the auxiliary transistor described above inrelation to all the embodiments can be a low voltage transistor or ahigh voltage transistor.

It will also be appreciated that terms such as “top” and “bottom”,“above” and “below”, “lateral” and “vertical”, and “under” and “over”,“front” and “behind”, “underlying”, etc. may be used in thisspecification by convention and that no particular physical orientationof the device as a whole is implied.

Although the disclosure has been described in terms of preferredembodiments as set forth above, it should be understood that theseembodiments are illustrative only and that the claims are not limited tothose embodiments. Those skilled in the art will be able to makemodifications and alternatives in view of the disclosure, which arecontemplated as falling within the scope of the appended claims. Eachfeature disclosed or illustrated in the present specification may beincorporated in the disclosure, whether alone or in any appropriatecombination with any other feature disclosed or illustrated herein.

REFERENCES

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Enhancement-mode HFET circuit arrangement having high power and highthreshold voltage. U.S. Pat. No. 8,368,121.

-   [21] GaN Systems, GN001 Application Guide Design with GaN    Enhancement mode HEMT,

What is claimed is:
 1. A III-nitride power semiconductor basedheterojunction device, comprising: an active heterojunction transistorformed on a substrate, the active heterojunction transistor comprising:a first III-nitride semiconductor region comprising a firstheterojunction comprising an active two dimensional carrier gas ofsecond conductivity type; a first terminal operatively connected to theIII-nitride semiconductor region; a second terminal laterally spacedfrom the first terminal and operatively connected to the III-nitridesemiconductor region; an active gate region formed over the III-nitridesemiconductor region, the active gate region being formed between thefirst terminal and the second terminal; an auxiliary heterojunctiontransistor formed on the said substrate or a further substrate, theauxiliary heterojunction transistor comprising: a second III-nitridesemiconductor region comprising a second heterojunction comprising anauxiliary two dimensional carrier gas of second conductivity type; afirst additional terminal operatively connected to the secondIII-nitride semiconductor region; a second additional terminal laterallyspaced from the first additional terminal and operatively connected tothe second III-nitride semiconductor region; an auxiliary gate regionformed over the second III-nitride semiconductor region, the auxiliarygate region being formed between the first additional terminal and thesecond additional terminal; wherein the first additional terminal isoperatively connected with the auxiliary gate region, and wherein thesecond additional terminal is operatively connected with the active gateregion; and wherein the auxiliary heterojunction transistor is a firstauxiliary heterojunction transistor, and wherein the heterojunctionpower device further comprises a second auxiliary heterojunctiontransistor which is operatively connected in parallel with the firstauxiliary transistor, and wherein the first additional terminal of thefirst auxiliary heterojunction transistor is operatively connected to asource terminal of the second auxiliary heterojunction transistor, andthe second additional terminal of the first auxiliary heterojunctiontransistor is operatively connected to a drain terminal of the secondauxiliary heterojunction transistor.
 2. A depletion mode III-nitridesemiconductor based heterojunction device, comprising: a substrate; aIII-nitride semiconductor region formed over the substrate, wherein theIII-nitride semiconductor region comprises a heterojunction comprisingat least one two-dimensional carrier gas of second conductivity type; afirst terminal operatively connected to the III-nitride semiconductorregion; a second terminal laterally spaced from the first terminal in afirst dimension and operatively connected to the III-nitridesemiconductor region; at least two highly doped semiconductor regions ofa first conductivity type formed over the III-nitride semiconductorregion, the at least two highly doped semiconductor regions being formedbetween the first terminal and the second terminal; and an active gateregion formed over the at least two highly doped semiconductor regions;wherein the at least two highly doped semiconductor regions are spacedfrom each other in a second dimension and wherein the second dimensionis perpendicular to the first dimension.
 3. A heterojunction powerdevice according to claim 1, further comprising an active Miller clampwhich comprises a logic inverter and an actively switched transistorwhich acts as a pull down network, and wherein the logic invertercomprises a resistor or resistive element and an enhancement modetransistor.
 4. A heterojunction chip having at least three terminals,the at least three terminals comprising a high voltage terminal, a lowvoltage terminal and a control terminal, wherein the heterojunction chipfurther comprises; at least one main power heterojunction transistor,wherein the at least one main power heterojunction transistor comprisesan internal gate terminal, a source terminal and a drain terminal,wherein the source terminal of the at least one main powerheterojunction transistor is operatively connected to the low voltageterminal and the drain terminal of the at least one main powerheterojunction transistor is operatively connected to the high voltageterminal; an auxiliary gate circuit comprising at least one firstlow-voltage heterojunction transistor, wherein the auxiliary gatecircuit is operatively connected to the internal gate terminal of the atleast one main power heterojunction transistor and to the controlterminal; a pull-down circuit comprising at least one non-linear elementand at least one second low-voltage heterojunction transistor, thenon-linear element comprising a potential divider for driving the gateterminal of the at least one second low-voltage heterojunctiontransistor, wherein the pull-down circuit is operatively connected to aninternal gate terminal of the at least one first low-voltageheterojunction transistor and to the source terminal of the at least onemain power heterojunction transistor; a current control circuitcomprising at least one resistor, wherein the current control circuit isoperatively connected to the control terminal and to the pull-downcircuit; and wherein the auxiliary gate and current control circuits atleast partially control a voltage and a current into the internal gateof the at least one main power heterojunction transistor; and whereinthe current control circuit at least partially controls a current intothe pull down circuit and at least partially determines a controlterminal voltage level at which the pull-down circuit actively pullsdown a gate voltage of the at least one first low-voltage heterojunctiontransistor to clamp a voltage of the internal gate of the at least onemain power heterojunction transistor.
 5. The heterojunction chip ofclaim 4, wherein the potential divider comprises at least one of aresistive, capacitive, diode or transistor elements; and the potentialdivider has at least one connection to an internal gate of the at leastone second low-voltage heterojunction transistor
 6. The heterojunctionchip of claim 4, wherein the potential divider is operatively connectedto at least one of the current control circuit, the internal gate of theat least one main power heterojunction transistor, and the controlterminal.
 7. The heterojunction chip of claim 4, wherein the currentcontrol circuit comprises at least one of: a resistor; at least onethird low-voltage heterojunction transistor; wherein each or both of theresistor and the at least one third low-voltage heterojunctiontransistor act as a current source and control the action of thepull-down circuit.
 8. The heterojunction chip of claim 7, wherein thecurrent control circuit further comprises at least one current mirrorcircuit.
 9. The heterojunction chip of claim 4, wherein at least one ofthe auxiliary gate circuit, the pull-down circuit and the currentcontrol circuit comprise at least one low-voltage depletion modeheterojunction transistor.
 10. The heterojunction chip of claim 4,wherein at least one of the auxiliary gate circuit, the pull-downcircuit and the current control circuit comprise at least one capacitor.11. The heterojunction chip of claim 4, wherein the heterojunction chipfurther comprises at least one monolithically integrated component, theat least one monolithically integrated component being one or more of aDC to DC converter circuit, a voltage regulator, and a gate voltage tologic signal clamping circuit.
 12. The heterojunction chip of claim 4,wherein at least one of the auxiliary gate circuit, the pull-downcircuit or the current control block are integrated under one or more ofthe internal gate, source and drain terminals of the at least one mainpower heterojunction transistor
 13. The heterojunction chip of claim 4,wherein the at least one main power heterojunction transistor comprisestwo main power heterojunction transistors connected in a half bridge,and wherein at least one of the two main power heterojunctiontransistors comprises at least one of the auxiliary gate circuit, thepull-down circuit and the current control circuit
 14. The heterojunctionchip of claim 4 wherein the at least one main power heterojunctiontransistor comprises four of the main power heterojunction transistorsconnected in a full bridge, and wherein at least one of the four mainpower heterojunction transistors comprises at least one of the auxiliarygate circuit, the pull-down circuit and the current control circuit. 15.The heterojunction chip of claim 4 wherein the at least one main powerheterojunction transistor comprises at least six main powerheterojunction transistors connected in a three phase half-bridgeconfiguration, and wherein at least one of the six main powerheterojunction transistors comprises at least one of the auxiliary gatecircuit, the pull-down circuit and the current control circuit
 16. Theheterojunction chip of claim 4, wherein the chip further comprises amonolithically integrated Miller clamp circuit, and wherein the Millerclamp circuit has one connection to the internal gate of the main powerheterojunction transistor and bypasses the pull-down circuit during thedevice off-state or turn-off transient.
 17. The heterojunction chip ofclaim 16, wherein the Miller clamp circuit comprises at least one Millerclamp low-voltage transistor, wherein a drain terminal of the at leastone Miller clamp low-voltage transistor is operatively connected to theinternal gate of the at least one main power heterojunction transistor18. The heterojunction chip of claim 17, wherein the internal gateterminal of the Miller clamp low-voltage transistor is operativelyconnected to an output of an additional circuit integrated on theheterojunction chip, wherein the additional circuit is at least one of:a over-current protection circuit; a under-voltage lock-out circuit; asupply-voltage over-voltage protection circuit; and a logic invertercircuit.
 19. The heterojunction chip of claim 4, wherein theheterojunction chip further comprises an monolithically integratedadditional circuit, and wherein the at least one second low-voltageheterojunction transistor is operatively connected to an output of themonolithically integrated additional circuit is at least one of: aover-current protection circuit; under-voltage lock-out circuit; asupply-voltage over-voltage protection circuit; and a logic invertercircuit.
 20. The heterojunction chip of claim 4, wherein the auxiliarygate circuit further comprises at least one additional low voltagetransistor, wherein an internal gate terminal and a source terminal ofthe at least one additional low voltage transistor are operativelyconnected to facilitate the turn-off of the at least one main powerheterojunction transistor.
 21. The heterojunction chip of claim 4,further comprising one or more monolithically integrated temperaturecompensated circuits, wherein the one or more monolithically integratedtemperature compensated circuit comprise: a low voltage heterojunctiontransistor; a first resistor connected in series with the low-voltageheterojunction transistor; and a second resistor connected in parallelwith the low-voltage heterojunction transistor; and wherein the one ormore monolithically integrated temperature compensated circuit eachreduce an effect of variations in temperature on a circuit behaviour ofconnected components.
 22. The heterojunction chip of claim 21, whereinthe one or more monolithically integrated temperature compensatedcircuits comprise part of at least one of the potential divider, theauxiliary gate circuit, the pull-down circuit and the current controlcircuit.
 23. A heterojunction power device according to claim 1, furthercomprising a shielding and/or decoupling structure disposed between theactive heterojunction transistor and the auxiliary heterojunctiontransistor.
 24. A heterojunction power device according to claim 23,wherein the shielding and/or decoupling structure comprises any of: oneor more layers of two-dimensional carrier gas of the first and/or secondconductivity type; one or more metal layers; and/or one or moreconductive layers; and wherein the shielding and/or decoupling structureis operatively connected to one of: the first terminal; a potential; orground.
 25. A heterojunction chip according to claim 4, furthercomprising a shielding and/or decoupling structure disposed between anytwo or more of: the at least one main power heterojunction transistor;the auxiliary gate circuit; the pull-down circuit; and/or the currentcontrol circuit.
 26. A heterojunction chip according to claim 25,wherein the shielding and/or decoupling structure comprises any of: oneor more layers of two-dimensional carrier gas of the first and/or secondconductivity type; one or more metal layers; and/or one or moreconductive layers; and wherein the shielding and/or decoupling structureis operatively connected to one of: the first terminal; a potential; orground.
 27. A heterojunction chip according to claim 4, wherein thepull-down circuit comprises one or more diodes in series with a DC oractively switched voltage source.
 28. A heterojunction chip according toclaim 4, wherein the pull-down circuit comprises a voltage source inseries with one more enhancement HEMTs; wherein each enhancement HEMTcomprises a gate terminal connected to the source terminal; and whereinthe voltage source is configured to be constant or variable; and,optionally wherein the voltage source is connected to an on-chip orexternal voltage regulator. 29: A heterojunction chip according to claim4, wherein the pull-down circuit comprises a voltage source in serieswith one or more enhancement HEMTs in a threshold multiplierarrangement; wherein the voltage source is configured to be constant orvariable; and, optionally wherein the voltage source is connected to anon-chip or external voltage regulator.
 30. A heterojunction chipaccording to claim 18, wherein the additional circuit comprises a logicinverter circuit, wherein at least one terminal of the logic invertercircuit is connected to a DC voltage through a decoupling circuit andwherein the decoupling circuit protects the said inverter from currentspikes or voltage spikes produced in the heterojunction chip.
 31. Aheterojunction power device according to claim 30, wherein thedecoupling circuit comprises one or more resistors, capacitors, currentsources, or other low voltage transistors.
 32. A heterojunction chipaccording to claim 4 wherein the current control circuit comprises atleast one low voltage transistor having at least one terminal connectedto a constant or variably controlled voltage level, wherein the saidvoltage level is provided from a monolithically integrated circuitand/or from an external circuit.
 33. A depletion mode III-nitridesemiconductor based heterojunction device according to claim 2, furthercomprising at least two rows of active gate regions each formed over theat least two highly doped semiconductor regions; wherein the depletionmode III-nitride semiconductor based heterojunction device has twothreshold levels, and wherein the depletion mode III-nitridesemiconductor based heterojunction device is configurable to activelyswitch between: (i) an off-state, wherein the gate voltage with respectto the source voltage is lower than the first threshold; (ii) a highresistance mode, wherein the gate voltage with respect to the sourcevoltage is between the first and second threshold levels; and (iii) alow resistance mode, wherein the when the gate voltage with respect tothe source voltage is higher than the second threshold.
 34. Aheterojunction power device according to claim 18, wherein theadditional circuit comprises a logic inverter circuit, wherein the logicinverter circuit comprises a current source circuit in series with anenhancement mode transistor; and optionally wherein the current sourcecomprises a depletion mode transistor and a resistive element. 35: Aheterojunction power device according to claim 18, wherein theadditional circuit comprises a logic inverter circuit, wherein the logicinverter circuit comprises multiple stages, wherein each stage comprisesan enhancement transistor on the low side with the gate connected to theinput signal and all stages comprise a pull-up circuit, of which all butthe one of the first stage are at least partially controlled by theprevious stages.
 36. A heterojunction chip according to claim 4, whereinthe heterojunction chip comprises at least one low voltage transistorthat is configured to provide an ENABLE function and/or a DISABLEfunction to the heterojunction chip, wherein the ENABLE function permitsthe operation of the heterojunction chip as normal, and wherein theDISABLE function transforms the chip into a high impedance mode state,disabling the operation of the heterojunction chip.
 37. A heterojunctionchip according to claim 4, wherein the current control circuit comprisesa circuit configured to create a voltage drop, wherein the circuitconfigured to create a voltage drop comprises one or more of: at leastone low-voltage diode; at least one low-voltage HEMT with gate connectedto source; at least one low-voltage enhancement mode HEMT comprising apotential divider connected between drain and source terminals of theHEMT, wherein a midpoint of the potential divider is connected to a gateterminal of the HEMT; and/or at least one voltage regulator.